TM4C129DNCZAD Datasheet, PDF (1477/1967 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C129DNCZAD Microcontroller
Register 25: I²C FIFO Status (I2CFIFOSTATUS), offset 0xF08
This register contains the real-time status of the RX and TX FIFOs.
I2C FIFO Status (I2CFIFOSTATUS)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
I2C 6 base: 0x400C.2000
I2C 7 base: 0x400C.3000
I2C 8 base: 0x400B.8000
I2C 9 base: 0x400B.9000
Offset 0xF08
Type RO, reset 0x0001.0005
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
RXABVTRIG RXFF
RXFE
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
TXBLWTRIG TXFF
TXFE
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
Bit/Field
31:19
18
Name
reserved
RXABVTRIG
Type
RO
RO
Reset
0x000
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
RX FIFO Above Trigger Level
Value Description
0 The number of bytes in RX FIFO is below the trigger level
programmed by the RXTRIG bit in the I2CFIFOCTL register
1 The number of bytes in the RX FIFO is above the trigger level
programmed by the RXTRIG bit in the I2CFIFOCTL register
17
RXFF
RO
0
RX FIFO Full
Value Description
0 The RX FIFO is not full.
1 The RX FIFO is full.
16
RXFE
RO
1
RX FIFO Empty
Value Description
0 The RX FIFO is not empty.
1 The RX FIFO is empty.
15:3
reserved
RO
0x000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
June 18, 2014
Texas Instruments-Production Data
1477