TMS320F280049M Datasheet, PDF (184/214 Pages) Texas Instruments – Piccolo Microcontrollers

TMS320F280049M
SPRS945 – JANUARY 2017
www.ti.com
6.5 Bus Architecture – Peripheral Connectivity
Table 6-5 lists a broad view of the peripheral and configuration register accessibility from each bus
master. Peripherals within peripheral frames 1 or 2 will all be mapped to the respective secondary master
as a group (if SPI is assigned to DMA, then LIN is also assigned to DMA).
Table 6-5. Bus Master Peripheral Access
PERIPHERALS
DMA
CLA
CPU
SYSTEM PERIPHERALS
CPU Timers
Y
System Configuration (WD, NMIWD, LPM, Peripheral Clock Gating)
Y
Device Capability, Peripheral Reset
Y
Clock and PLL Configuration
Y
Flash Configuration
Y
Reset Configuration
Y
GPIO Pin Mapping and Configuration
GPIO Data⁽¹⁾
Y
Y
Y
DMA and CLA Trigger Source Select
Y
CONTROL PERIPHERALS
ePWM/HRPWM
Y
Y
Y
eCAP
eQEP ⁽²⁾
Y
Y
Y
Y
Y
Y
SDFM
Y
Y
Y
ANALOG PERIPHERALS
Analog System Control
Y
ADC Configuration
Y
Y
ADC Result
CMPSS ⁽²⁾
DAC ⁽²⁾
PGA ⁽²⁾
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
COMMUNICATION PERIPHERALS
CAN
Y
Y
SPI
Y
Y
Y
I2C
Y
PMBus
Y
Y
Y
SCI
Y
LIN
Y
Y
Y
(1) The GPIO Data Registers are unique for the CPU and CLA. When the GPIO Pin Mapping Register is configured to assign a GPIO to a
particular master, the respective GPIO Data Register will control the GPIO. See the General-Purpose Input/Output (GPIO) chapter of the
TMS320F28004x Piccolo Microcontrollers Technical Reference Manual for more details.
(2) These modules are accessible from DMA but cannot trigger a DMA transfer.
184 Detailed Description
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