TMS320F280049M Datasheet, PDF (182/214 Pages) Texas Instruments – Piccolo Microcontrollers

TMS320F280049M
SPRS945 – JANUARY 2017
www.ti.com
Table 6-2. Addresses of Flash Sectors (continued)
SECTOR
TI OTP ECC Bank 0
TI OTP ECC Bank 1
User-configurable DCSM OTP ECC Bank 0
User-configurable DCSM OTP ECC Bank 1
Flash ECC Bank 0
Flash ECC Bank 1
SIZE
START ADDRESS
FLASH ECC LOCATIONS
128 x 16
0x0107 0000
128 x 16
0x0107 0080
128 x 16
0x0107 1000
128 x 16
0x0107 1080
8K x 16
0x0108 0000
8K x 16
0x0108 2000
END ADDRESS
0x0107 007F
0x0107 00FF
0x0107 107F
0x0107 10FF
0x0108 1FFF
0x0108 3FFF
6.3.3 Memory Types
6.3.3.1 Dedicated RAM (Mx RAM)
The CPU subsystem has two dedicated ECC-capable RAM blocks: M0 and M1. These memories are
small nonsecure blocks that are tightly coupled with the CPU (that is, only the CPU has access to them).
6.3.3.2 Local Shared RAM (LSx RAM)
RAM blocks which are dedicated to each subsystem and are accessible only to its CPU and CLA, are
called local shared RAMs (LSx RAMs).
All LSx RAM blocks have parity. These memories are secure and have the access protection (CPU
write/CPU fetch) feature.
By default, these memories are dedicated only to the CPU, and the user could choose to share these
memories with the CLA by configuring the MSEL_LSx bit field in the LSxMSEL registers appropriately
(see Table 6-3).
MSEL_LSx
00
01
01
Table 6-3. Master Access for LSx RAM
(With Assumption That all Other Access Protections are Disabled)
CLAPGM_LSx
X
0
1
CPU ALLOWED
ACCESS
All
All
Emulation Read
Emulation Write
CLA1 ALLOWED
ACCESS
COMMENT
–
LSx memory is configured
as CPU dedicated RAM.
Data Read
Data Write
Emulation Data Read
Emulation Data Write
LSx memory is shared
between CPU and CLA1.
Fetch Only
Emulation Program Read
Emulation Program Write
LSx memory is CLA1
program memory.
182 Detailed Description
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