TMS320F280049M Datasheet, PDF (171/214 Pages) Texas Instruments – Piccolo Microcontrollers

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TMS320F280049M
SPRS945 – JANUARY 2017
5.11.7 Fast Serial Interface (FSI)
The Fast Serial Interface (FSI) module is a serial communication peripheral capable of reliable high-speed
communication across isolation devices. Galvanic isolation devices are used in situations where two
different electronic circuits, which do not have common power and ground connections, must exchange
information. Though isolation devices facilitate these signal communications, they can also introduce a
large delay on the signal lines and add skew between the signals. The FSI is designed specifically to
ensure reliable high-speed communication for system scenarios that involve communication across
isolation barriers without adding components.
The FSI consists of independent transmitter (FSITX) and receiver (FSIRX) cores. The FSITX and FSIRX
cores are configured and operated independently.
The FSI module includes the following features:
• Independent transmitter and receiver cores
• Source-synchronous transmission
• Dual data rate (DDR)
• One or two data lines
• Programmable data length
• Skew adjustment block to compensate for board and system delay mismatches
• Frame error detection
• Programmable frame tagging for message filtering
• Hardware ping to detect line breaks during communication (ping watchdog)
• Two interrupts per FSI core
• Externally triggered frame generation
• Hardware- or software-calculated CRC
• Embedded ECC computation module
• Register write protection
• DMA support
• CLA task triggering
5.11.7.1 FSI Transmitter
The FSI transmitter module handles the framing of data, CRC generation, and signal generation of
TXCLK, TXD0, and TXD1, as well as interrupt generation. The operation of the transmitter core is
controlled and configured through programmable control registers. The transmitter control registers allow
the CPU (or the CLA) to program, control, and monitor the operation of the FSI receiver. The transmit data
buffer is accessible by the CPU, CLA, and the DMA.
The transmitter has the following features:
• Automated ping frame generation
• Externally triggered ping frames
• Externally triggered data frames
• Software-configurable frame lengths
• 16-word data buffer
• Data buffer underrun and overrun detection
• Hardware-generated CRC on data bits
• Software ECC calculation on select data
• DMA support
• CLA task triggering
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Specifications 171