LMH6504 Datasheet, PDF (17/29 Pages) National Semiconductor (TI) – Wideband, Low Power, Variable Gain Amplifier

LMH6504
www.ti.com
SNOSA96D – NOVEMBER 2003 – REVISED MARCH 2013
TRANSMISSION LINE MATCHING
One method for matching the characteristic impedance of a transmission line is to place the appropriate resistor
at the input or output of the amplifier. Figure 46 shows a typical circuit configuration for matching transmission
lines.
V_G
R_S
SIGNAL
INPUT
+-
Z_O
R_I
C_O
1
2
6
LMH6504
3
7
R_O
4
R_G
R_F
Z_O
OUTPUT
R_T
Figure 46. TRANSMISSION LINE MATCHING
The resistors R_S, R_I, R_O, and R_T are equal to the characteristic impedance, Z_O, of the transmission line or cable.
Use C_O to match the output transmission line over a greater frequency range. It compensates for the increase of
the op amp’s output impedance with frequency.
MINIMIZING PARASITIC EFFECTS ON SMALL SIGNAL BANDWIDTH
The best way to minimize parasitic effects is to use surface mount components and to minimize lead lengths and
component distance from the LMH6504. For designs utilizing through-hole components, specifically axial
resistors, resistor self-capacitance should be considered. Example: the average magnitude of parasitic
capacitance of RN55D 1% metal film resistors is about 0.15 pF with variations of as much as 0.1 pF between
lots. Given the LMH6504’s extended bandwidth, these small parasitic reactance variations can cause
measurable frequency response variations in the highest octave. We therefore recommend the use of surface
mount resistors to minimize these parasitic reactance effects.
RECOMMENDATIONS
Here are some recommendations to avoid problems and to get the best performance:
• Do not place a capacitor across R_F. However, an appropriately chosen series RC combination could be used
to shape the frequency response.
• Keep traces connecting R_F separated and as short as possible
• Place a small resistor (20-50Ω) between the output and C_L
• Cut away the ground plane, if any, under R_G
• Keep decoupling capacitors as close as possible to the LMH6504.
• Connect pin 2 through a minimum resistance of 25Ω.
ADJUSTING OFFSETS AND DC LEVEL SHIFTING
Offsets can be broken into two parts: an input-referred term and an output-referred term. These errors can be
trimmed using the circuit in Figure 47. First set V_G to 0V and adjust the trim pot R₄ to null the offset voltage at the
output. This will eliminate the output stage offsets. Next set V_G to 2V and adjust the trim pot R₁ to null the offset
voltage at the output. This will eliminate the input stage offsets.
Copyright © 2003–2013, Texas Instruments Incorporated
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