LM3S1439_16 Datasheet, PDF (162/699 Pages) Texas Instruments – Stellaris LM3S1439 Microcontroller

JTAG Interface
Figure 4-2. Test Access Port State Machine
Test Logic Reset
1
0
Run Test Idle
1
0
Select DR Scan
1
0
Capture DR
1
0
Shift DR
1
0
Exit 1 DR
1
0
Pause DR
1
0
Exit 2 DR
0
1
Update DR
10
Select IR Scan
1
0
Capture IR
1
0
Shift IR
1
0
Exit 1 IR
1
0
Pause IR
1
0
Exit 2 IR
0
1
Update IR
10
4.3.3
4.3.4
Shift Registers
The Shift Registers consist of a serial shift register chain and a parallel load register. The serial shift
register chain samples specific information during the TAP controller’s CAPTURE states and allows
this information to be shifted out of TDO during the TAP controller’s SHIFT states. While the sampled
data is being shifted out of the chain on TDO, new data is being shifted into the serial shift register
on TDI. This new data is stored in the parallel load register during the TAP controller’s UPDATE
states. Each of the shift registers is discussed in detail in “Register Descriptions” on page 165.
Operational Considerations
There are certain operational considerations when using the JTAG module. Because the JTAG pins
can be programmed to be GPIOs, board configuration and reset conditions on these pins must be
considered. In addition, because the JTAG module has integrated ARM Serial Wire Debug, the
method for switching between these two operational modes is described below.
162
July 15, 2014
Texas Instruments-Production Data