LM3S1439_16 Datasheet, PDF (11/699 Pages) Texas Instruments – Stellaris LM3S1439 Microcontroller

Stellaris^® LM3S1439 Microcontroller
Figure 13-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 476
Figure 13-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 477
Figure 13-10. MICROWIRE Frame Format (Single Frame) ........................................................ 478
Figure 13-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 479
Figure 13-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 479
Figure 14-1. I²C Block Diagram ............................................................................................. 508
Figure 14-2. I²C Bus Configuration ........................................................................................ 509
Figure 14-3. START and STOP Conditions ............................................................................. 509
Figure 14-4. Complete Data Transfer with a 7-Bit Address ....................................................... 510
Figure 14-5. R/S Bit in First Byte ............................................................................................ 510
Figure 14-6. Data Validity During Bit Transfer on the I²C Bus ................................................... 510
Figure 14-7. Master Single SEND .......................................................................................... 514
Figure 14-8. Master Single RECEIVE ..................................................................................... 515
Figure 14-9. Master Burst SEND ........................................................................................... 516
Figure 14-10. Master Burst RECEIVE ...................................................................................... 517
Figure 14-11. Master Burst RECEIVE after Burst SEND ............................................................ 518
Figure 14-12. Master Burst SEND after Burst RECEIVE ............................................................ 519
Figure 14-13. Slave Command Sequence ................................................................................ 520
Figure 15-1. Analog Comparator Module Block Diagram ......................................................... 544
Figure 15-2. Structure of Comparator Unit .............................................................................. 545
Figure 15-3. Comparator Internal Reference Structure ............................................................ 546
Figure 16-1. PWM Unit Diagram ............................................................................................ 557
Figure 16-2. PWM Module Block Diagram .............................................................................. 558
Figure 16-3. PWM Count-Down Mode .................................................................................... 560
Figure 16-4. PWM Count-Up/Down Mode .............................................................................. 560
Figure 16-5. PWM Generation Example In Count-Up/Down Mode ........................................... 561
Figure 16-6. PWM Dead-Band Generator ............................................................................... 561
Figure 17-1. QEI Block Diagram ............................................................................................ 596
Figure 17-2. Quadrature Encoder and Velocity Predivider Operation ........................................ 598
Figure 18-1. 100-Pin LQFP Package Pin Diagram .................................................................. 613
Figure 18-2. 108-Ball BGA Package Pin Diagram (Top View) ................................................... 614
Figure 21-1. Load Conditions ................................................................................................ 647
Figure 21-2. JTAG Test Clock Input Timing ............................................................................. 650
Figure 21-3. JTAG Test Access Port (TAP) Timing .................................................................. 650
Figure 21-4. JTAG TRST Timing ............................................................................................ 650
Figure 21-5. External Reset Timing (RST) .............................................................................. 651
Figure 21-6. Power-On Reset Timing ..................................................................................... 651
Figure 21-7. Brown-Out Reset Timing .................................................................................... 652
Figure 21-8. Software Reset Timing ....................................................................................... 652
Figure 21-9. Watchdog Reset Timing ..................................................................................... 652
Figure 21-10. Hibernation Module Timing ................................................................................. 653
Figure 21-11. ADC Input Equivalency Diagram ......................................................................... 654
Figure 21-12. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing
Measurement .................................................................................................... 655
Figure 21-13. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ................. 656
Figure 21-14. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ..................................... 656
Figure 21-15. I²C Timing ......................................................................................................... 657
Figure D-1. Stellaris LM3S1439 100-Pin LQFP Package Dimensions ..................................... 687
July 15, 2014
11
Texas Instruments-Production Data