SM73201 Datasheet, PDF (16/21 Pages) Texas Instruments – 16-Bit, 50 to 250 kSPS, Differential Input, MicroPower ADC

Applications Information
OPERATING CONDITIONS
We recommend that the following conditions be observed for
operation of the SM73201:
−40°C ≤ T_A ≤ +85°C
+4.5V ≤ V_A ≤ +5.5V
+2.7V ≤ V_IO ≤ +5.5V
+0.5V ≤ V_REF ≤ +5.5V
1 MHz ≤ f_SCLK ≤ 5 MHz
V_CM: See Section 2.3
4.0 ANALOG INPUT CONSIDERATIONS
As stated previously in Section 2.5, it is not critical for the
performance of the SM73201 to filter out the voltage spike
that occurs when the SM73201 enters acquisition (t_ACQ) mode
at the end of the conversion window. However, it is critical that
a system designer ensures that the transients of the spike
settle out within t_ACQ. The burden of this task can be placed
on the analog source itself or the burden can be shared by
the source and an external capacitor, C_EXT as shown in Figure
13. The external capacitor acts as a local charge reservoir for
the internal sampling capacitor and thus reduces the size of
the voltage spike. For low frequency analog sources such as
sensors with DC-like output behaviors, C_EXT values greater
than 1 nF are recommended. However, some sensors and
signal conditioning circuitry will not be able to maintain their
stability in the presence of the external capacitive load. In
these instances, a series resistor (R_EXT) is recommended.
The magnitude of R_EXT is dependent on the output capability
of the analog source and the settling requirement of the ADC.
Independent of the presence of an external capacitor, the
system designer always has the option of lowering the sample
rate of the SM73201 which directly controls the amount of
time allowed for the voltage spike to settle. The slower the
sample rate, the longer the t_ACQ time or settling time. This is
possible with the SM73201 since the converter enters t_ACQ at
the end of the prior conversion and thus is tracking the analog
input source the entire time between conversions.
5.0 POWER CONSUMPTION
The architecture, design, and fabrication process allow the
SM73201 to operate at conversion rates up to 250 kSPS while
consuming very little power. The SM73201 consumes the
least amount of power while operating in acquisition (power-
down) mode. For applications where power consumption is
critical, the SM73201 should be operated in acquisition mode
as often as the application will tolerate. To further reduce
power consumption, stop the SCLK while CS is high.
5.1 Short Cycling
Short cycling refers to the process of halting a conversion af-
ter the last needed bit is outputted. Short cycling can be used
to lower the power consumption in those applications that do
not need a full 16-bit resolution, or where an analog signal is
being monitored until some condition occurs. In some circum-
stances, the conversion could be terminated after the first few
bits. This will lower power consumption in the converter since
the SM73201 spends more time in acquisition mode and less
time in conversion mode.
Short cycling is accomplished by pulling CS high after the last
required bit is received from the SM73201 output. This is pos-
sible because the SM73201 places the latest converted data
bit on D_OUT as it is generated. If only 10-bits of the conversion
result are needed, for example, the conversion can be termi-
nated by pulling CS high after the 10^th bit has been clocked
out.
5.2 Burst Mode Operation
Normal operation of the SM73201 requires the SCLK fre-
quency to be 20 times the sample rate and the CS rate to be
the same as the sample rate. However, in order to minimize
power consumption in applications requiring sample rates be-
low 250 kSPS, the SM73201 should be run with an SCLK
frequency of 5 MHz and a CS rate as slow as the system
requires. When this is accomplished, the SM73201 is oper-
ating in burst mode. The SM73201 enters into acquisition
mode at the end of each conversion, minimizing power con-
sumption. This causes the converter to spend the longest
possible time in acquisition mode. Since power consumption
scales directly with conversion rate, minimizing power con-
sumption requires determining the lowest conversion rate that
will satisfy the requirements of the system.
6.0 PCB LAYOUT AND CIRCUIT CONSIDERATIONS
For best performance, care should be taken with the physical
layout of the printed circuit board. This is especially true with
a low V_REF or when the conversion rate is high. At high clock
rates there is less time for settling, so it is important that any
noise settles out before the conversion begins.
6.1 Analog and Digital Power Supplies
Any ADC architecture is sensitive to spikes on the power sup-
ply, reference, and ground pins. These spikes may originate
from switching power supplies, digital logic, high power de-
vices, and other sources. Power to the SM73201 should be
clean and well bypassed. A 0.1 µF ceramic bypass capacitor
and a 1 µF to 10 µF capacitor should be used to bypass the
SM73201 supply, with the 0.1 µF capacitor placed as close to
the SM73201 package as possible.
Since the SM73201 has both the V_A and V_IO pins, the user
has three options on how to connect these pins. The first op-
tion is to tie V_A and V_IO together and power them with the same
power supply. This is the most cost effective way of powering
the SM73201 but is also the least ideal. As stated previously,
noise from V_IO can couple into V_A and adversely affect per-
formance. The other two options involve the user powering
V_A and V_IO with separate supply voltages. These supply volt-
ages can have the same amplitude or they can be different.
V_A can be set to any value between +4.5V and +5.5V; while
V_IO can be set to any value between +2.7V and +5.5V.
Best performance will typically be achieved with V_A operating
at 5V and V_IO at 3V. Operating V_A at 5V offers the best linearity
and dynamic performance when V_REF is also set to 5V; while
operating V_IO at 3V reduces the power consumption of the
digital logic. Operating the digital interface at 3V also has the
added benefit of decreasing the noise created by charging
and discharging the capacitance of the digital interface pins.
6.2 Voltage Reference
The reference source must have a low output impedance and
needs to be bypassed with a minimum capacitor value of 0.1
µF. A larger capacitor value of 1 µF to 10 µF placed in parallel
with the 0.1 µF is preferred. While the SM73201 draws very
little current from the reference on average, there are higher
instantaneous current spikes at the reference.
V_REF of the SM73201, like all A/D converters, does not reject
noise or voltage variations. Keep this in mind if V_REF is derived
from the power supply. Any noise and/or ripple from the sup-
ply that is not rejected by the external reference circuitry will
appear in the digital results. The use of an active reference
source is recommended. The LM4040 and LM4050 shunt ref-
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