SM73201 Datasheet, PDF (12/21 Pages) Texas Instruments – 16-Bit, 50 to 250 kSPS, Differential Input, MicroPower ADC

Functional Description
The SM73201 is a 16-bit, 50 kSPS to 250 kSPS sampling
Analog-to-Digital (A/D) converter. The converter uses a suc-
cessive approximation register (SAR) architecture based up-
on capacitive redistribution containing an inherent sample-
and-hold function. The differential nature of the analog inputs
is maintained from the internal sample-and-hold circuits
throughout the A/D converter to provide excellent common-
mode signal rejection.
The SM73201 operates from independent analog and digital
supplies. The analog supply (V_A) can range from 4.5V to 5.5V
and the digital input/output supply (V_IO) can range from 2.7V
to 5.5V. The SM73201 utilizes an external reference (V_REF),
which can be any voltage between 0.5V and V_A. The value of
V_REF determines the range of the analog input, while the ref-
erence input current (I_REF) depends upon the conversion rate.
The analog input is presented to two input pins: +IN and –IN.
Upon initiation of a conversion, the differential input at these
pins is sampled on the internal capacitor array. The inputs are
disconnected from the internal circuitry while a conversion is
in progress. The SM73201 features a zero-power track mode
(ZPTM) where the ADC is consuming the minimum amount
of power (Power-Down Mode) while the internal sampling ca-
pacitor array is tracking the applied analog input voltage. The
converter enters ZPTM at the end of each conversion window
and experiences no delay when the ADC enters into Conver-
sion Mode. This feature allows the user an easy means for
optimizing system performance based on the settling capa-
bility of the analog source while minimizing power consump-
tion. ZPTM is exercised by bringing chip select bar (CS) high
or when CS is held low after the conversion is complete (after
the 18^th falling edge of the serial clock).
The SM73201 communicates with other devices via a Serial
Peripheral Interface (SPI™), a synchronous serial interface
that operates using three pins: chip select bar (CS), serial
clock (SCLK), and serial data out (D_OUT). The external SCLK
controls data transfer and serves as the conversion clock. The
duty cycle of SCLK is essentially unimportant, provided the
minimum clock high and low times are met. The minimum
SCLK frequency is set by internal capacitor leakage. Each
conversion requires a minimum of 18 SCLK cycles to com-
plete. If less than 16 bits of conversion data are required,
CS can be brought high at any point during the conversion.
This procedure of terminating a conversion prior to comple-
tion is commonly referred to as short cycling.
The digital conversion result is clocked out by the SCLK input
and is provided serially, most significant bit (MSB) first, at the
D_OUT pin. The digital data that is provided at the D_OUT pin is
that of the conversion currently in progress and thus there is
no pipe line delay or latency.
1.0 REFERENCE INPUT (V_REF)
The externally supplied reference voltage (V_REF) sets the
analog input range. The SM73201 will operate with V_REF in
the range of 0.5V to V_A.
Operation with V_REF below 2.5V is possible with slightly di-
minished performance. As V_REF is reduced, the range of
acceptable analog input voltages is reduced. Assuming a
proper common-mode input voltage (V_CM), the differential
peak-to-peak input range is limited to (2 x V_REF). See Section
2.3 for more details.
Reducing V_REF also reduces the size of the least significant
bit (LSB). For example, the size of one LSB is equal to [(2 x
V_REF) / 2ⁿ], which is 152.6 µV where n is 16 bits and V_REF is
5V. When the LSB size goes below the noise floor of the
SM73201, the noise will span an increasing number of codes
and overall performance will suffer. Dynamic signals will have
their SNR degrade; while, D.C. measurements will have their
code uncertainty increase. Since the noise is Gaussian in na-
ture, the effects of this noise can be reduced by averaging the
results of a number of consecutive conversions.
V_REF and analog inputs (+IN and -IN) are connected to the
capacitor array through a switch matrix when the input is
sampled. Hence, I_REF, I_+IN, and I_-IN are a series of transient
spikes that occur at a frequency dependent on the operating
sample rate of the SM73201.
I_REF changes only slightly with temperature. See the curves,
“Reference Current vs. SCLK Frequency” and “Reference
Current vs. Temperature” in the Typical Performance Curves
section for additional details.
2.0 ANALOG SIGNAL INPUTS
The SM73201 has a differential input where the effective input
voltage that is digitized is (+IN) − (−IN).
2.1 Differential Input Operation
The transfer curve of the SM73201 for a fully differential input
signal is shown in Figure 7. A positive full scale output code
(0111 1111 1111 1111b or 7FFFh or 32,767d) will be obtained
when (+IN) − (−IN) is greater than or equal to (V_REF − 1 LSB).
A negative full scale code (1000 0000 0000 0000b or 8000h
or -32,768d) will be obtained when [(+IN) − (−IN)] is less than
or equal to (−V_REF + 1 LSB). This ignores gain, offset and
linearity errors, which will affect the exact differential input
voltage that will determine any given output code.
FIGURE 7. ADC Transfer Curve
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