SM73201 Datasheet, PDF (15/21 Pages) Texas Instruments – 16-Bit, 50 to 250 kSPS, Differential Input, MicroPower ADC

3.0 SERIAL DIGITAL INTERFACE
The SM73201 communicates via a synchronous 3-wire serial
interface as shown in Figure 1 or re-shown in Figure 14 for
convenience. CS, chip select bar, initiates conversions and
frames the serial data transfers. SCLK (serial clock) controls
both the conversion process and the timing of the serial data.
D_OUT is the serial data output pin, where a conversion result
is sent as a serial data stream, MSB first.
A serial frame is initiated on the falling edge of CS and ends
on the rising edge of CS. The SM73201's D_OUT pin is in a high
impedance state when CS is high and for the first clock period
after CS is asserted; D_OUT is active for the remainder of time
when CS is asserted.
The SM73201 samples the differential input upon the asser-
tion of CS. Assertion is defined as bringing the CS pin to a
logic low state. For the first 17 periods of the SCLK following
the assertion of CS, the SM73201 is converting the analog
input voltage. On the 18^th falling edge of SCLK, the SM73201
enters acquisition (t_ACQ) mode. For the next three periods of
SCLK, the SM73201 is operating in acquisition mode where
the ADC input is tracking the analog input signal applied
across +IN and -IN. During acquisition mode, the SM73201
is consuming a minimal amount of power.
The SM73201 can enter conversion mode (t_CONV) under three
different conditions. The first condition involves CS going low
(asserted) with SCLK high. In this case, the SM73201 enters
conversion mode on the first falling edge of SCLK after CS is
asserted. In the second condition, CS goes low with SCLK
low. Under this condition, the SM73201 automatically enters
conversion mode and the falling edge of CS is seen as the
first falling edge of SCLK. In the third condition, CS and SCLK
go low simultaneously and the SM73201 enters conversion
mode. While there is no timing restriction with respect to the
falling edges of CS and SCLK, there are minimum setup and
hold time requirements for the falling edge of CS with respect
to the rising edge of SCLK. See Figure 5 in the Timing Dia-
gram section for more information.
3.1 CS Input
The CS (chip select bar) input is active low and is CMOS
compatible. The SM73201 enters conversion mode when
CS is asserted and the SCLK pin is in a logic low state. When
CS is high, the SM73201 is always in acquisition mode and
thus consuming the minimum amount of power. Since CS
must be asserted to begin a conversion, the sample rate of
the SM73201 is equal to the assertion rate of CS.
Proper operation requires that the fall of CS not occur simul-
taneously with a rising edge of SCLK. If the fall of CS occurs
during the rising edge of SCLK, the data might be clocked out
one bit early. Whether or not the data is clocked out early
depends upon how close the CS transition is to the SCLK
transition, the device temperature, and the characteristics of
the individual device. To ensure that the MSB is always
clocked out at a given time (the 3^rd falling edge of SCLK), it is
essential that the fall of CS always meet the timing require-
ment specified in the Timing Specification table.
3.2 SCLK Input
The SCLK (serial clock) is used as the conversion clock to
shift out the conversion result. SCLK is CMOS compatible.
Internal settling time requirements limit the maximum clock
frequency while internal capacitor leakage limits the minimum
clock frequency. The SM73201 offers guaranteed perfor-
mance with the clock rates indicated in the electrical table.
The SM73201 enters acquisition mode on the 18^th falling
edge of SCLK during a conversion frame. Assuming that the
LSB is clocked into a controller on the 18^th rising edge of
SCLK, there is a minimum acquisition time period that must
be met before a new conversion frame can begin. Other than
the 18^th rising edge of SCLK that was used to latch the LSB
into a controller, there is no requirement for the SCLK to tran-
sition during acquisition mode. Therefore, it is acceptable to
idle SCLK after the LSB has been latched into the controller.
3.3 Data Output
The data output format of the SM73201 is two’s complement
as shown in Figure 7. This figure indicates the ideal output
code for a given input voltage and does not include the effects
of offset, gain error, linearity errors, or noise. Each data output
bit is output on the falling edges of SCLK. D_OUT is in a high
impedance state for the 1^st falling edge of SCLK while the
2^nd SCLK falling edge clocks out a leading zero. The 3^rd to
18^th SCLK falling edges clock out the conversion result, MSB
first.
While most receiving systems will capture the digital output
bits on the rising edges of SCLK, the falling edges of SCLK
may be used to capture the conversion result if the minimum
hold time for D_OUT is acceptable. See Figure 4 for D_OUT hold
(t_DH) and access (t_DA) times.
D_OUT is enabled on the second falling edge of SCLK after the
assertion of CS and is disabled on the rising edge of CS. If
CS is raised prior to the 18^th falling edge of SCLK, the current
conversion is aborted and D_OUT will go into its high impedance
state. A new conversion will begin when CS is driven LOW.
FIGURE 14. SM73201 Single Conversion Timing Diagram
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