DS90CR287MTDX Datasheet, PDF (15/24 Pages) Texas Instruments – DS90CR287/DS90CR288A +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link - 85MHz

DS90CR287, DS90CR288A
www.ti.com
SNLS056G – OCTOBER 1999 – REVISED MARCH 2013
CLOCK JITTER: The CHANNEL LINK devices employ a PLL to generate and recover the clock transmitted
across the LVDS interface. The width of each bit in the serialized LVDS data stream is one-seventh the clock
period. For example, a 85 MHz clock has a period of 11.76 ns which results in a data bit width of 1.68 ns.
Differential skew (Δt within one differential pair), interconnect skew (Δt of one differential pair to another) and
clock jitter will all reduce the available window for sampling the LVDS serial data streams. Care must be taken to
ensure that the clock input to the transmitter be a clean low noise signal. Individual bypassing of each V_CC to
ground will minimize the noise passed on to the PLL, thus creating a low jitter LVDS clock. These measures
provide more margin for channel-to-channel skew and interconnect skew as a part of the overall jitter/skew
budget.
INPUT CLOCK: The input clock should be present at all times when the part in enabled. If the clock is stopped,
the PWR DOWN pin should be asserted to disable the PLL. Once the clock is active again, the part can then be
enabled. Do not enable the part without a clock present.
COMMON-MODE vs. DIFFERENTIAL MODE NOISE MARGIN: The typical signal swing for LVDS is 300 mV
centered at +1.2V. The CHANNEL LINK receiver supports a 100 mV threshold therefore providing approximately
200 mV of differential noise margin. Common-mode protection is of more importance to the system's operation
due to the differential data transmission. LVDS supports an input voltage range of Ground to +2.4V. This allows
for a ±1.0V shifting of the center point due to ground potential differences and common-mode noise.
TRANSMITTER INPUT CLOCK: The transmitter input clock must always be present when the device is enabled
(PWR DOWN = HIGH). If the clock is stopped, the PWR DOWN pin must be used to disable the PLL. The PWR
DOWN pin must be held low until after the input clock signal has been reapplied. This will ensure a proper device
reset and PLL lock to occur.
POWER SEQUENCING AND POWERDOWN MODE: Outputs of the CHANNEL LINK transmitter remain in TRI-
STATE until the power supply reaches 2V. Clock and data outputs will begin to toggle 10 ms after V_CC has
reached 3V and the Powerdown pin is above 1.5V. Either device may be placed into a powerdown mode at any
time by asserting the Powerdown pin (active low). Total power dissipation for each device will decrease to 5 μW
(typical).
The transmitter input clock may be applied prior to powering up and enabling the transmitter. The transmitter
input clock may also be applied after power up; however, the use of the PWR DOWN pin is required. Do not
power up and enable (PWR DOWN = HIGH) the transmitter without a valid clock signal applied to the TxCLK IN
pin.
The CHANNEL LINK chipset is designed to protect itself from accidental loss of power to either the transmitter or
receiver. If power to the transmit board is lost, the receiver clocks (input and output) stop. The data outputs
(RxOUT) retain the states they were in when the clocks stopped. When the receiver board loses power, the
receiver inputs are shorted to V_CC through an internal diode. Current is limited (5 mA per input) by the fixed
current mode drivers, thus avoiding the potential for latchup when powering the device.
Copyright © 1999–2013, Texas Instruments Incorporated
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