DS90CR287MTDX Datasheet, PDF (12/24 Pages) Texas Instruments – DS90CR287/DS90CR288A +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link - 85MHz

DS90CR287, DS90CR288A
SNLS056G – OCTOBER 1999 – REVISED MARCH 2013
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DS90CR287 DGG (TSSOP) Package PIN DESCRIPTION — Channel Link Transmitter
Pin Name
I/O No.
Description
TxIN
I 28 TTL level input.
TxOUT+
O 4 Positive LVDS differential data output.
TxOUT−
O 4 Negative LVDS differential data output.
TxCLK IN
I 1 TTL level clock input. The rising edge acts as data strobe. Pin name TxCLK IN. See APPLICATIONS
INFORMATION section.
TxCLK OUT+
O 1 Positive LVDS differential clock output.
TxCLK OUT−
O 1 Negative LVDS differential clock output.
PWR DOWN
I 1 TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power down. See
APPLICATIONS INFORMATION section.
V_CC
GND
I 4 Power supply pins for TTL inputs.
I 5 Ground pins for TTL inputs.
PLL V_CC
PLL GND
I 1 Power supply pin for PLL.
I 2 Ground pins for PLL.
LVDS V_CC
LVDS GND
I 1 Power supply pin for LVDS outputs.
I 3 Ground pins for LVDS outputs.
DS90CR288A DGG (TSSOP) Package PIN DESCRIPTION — Channel Link Receiver
Pin Name
I/O No.
Description
RxIN+
I 4 Positive LVDS differential data inputs.
RxIN−
I 4 Negative LVDS differential data inputs.
RxOUT
O 28 TTL level data outputs.
RxCLK IN+
I 1 Positive LVDS differential clock input.
RxCLK IN−
I 1 Negative LVDS differential clock input.
RxCLK OUT
O 1 TTL level clock output. The rising edge acts as data strobe. Pin name RxCLK OUT.
PWR DOWN
I 1 TTL level input. When asserted (low input) the receiver outputs are low.
V_CC
GND
I 4 Power supply pins for TTL outputs.
I 5 Ground pins for TTL outputs.
PLL V_CC
PLL GND
I 1 Power supply for PLL.
I 2 Ground pin for PLL.
LVDS V_CC
LVDS GND
I 1 Power supply pin for LVDS inputs.
I 3 Ground pins for LVDS inputs.
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