DS90CR287MTDX Datasheet, PDF (14/24 Pages) Texas Instruments – DS90CR287/DS90CR288A +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link - 85MHz

DS90CR287, DS90CR288A
SNLS056G – OCTOBER 1999 – REVISED MARCH 2013
www.ti.com
line of the differential pair. Care should be taken to ensure that the differential trace impedance match the
differential impedance of the selected physical media (this impedance should also match the value of the
termination resistor that is connected across the differential pair at the receiver's input). Finally, the location of
the CHANNEL LINK TxOUT/RxIN pins should be as close as possible to the board edge so as to eliminate
excessive pcb runs. All of these considerations will limit reflections and crosstalk which adversely effect high
frequency performance and EMI.
INPUTS: The TxIN and control pin inputs are compatible with LVTTL and LVCMOS levels. This pins are not 5V
tolerant.
UNUSED INPUTS: All unused inputs at the TxIN inputs of the transmitter may be tied to ground or left no
connect. All unused outputs at the RxOUT outputs of the receiver must then be left floating.
TERMINATION: Use of current mode drivers requires a terminating resistor across the receiver inputs. The
CHANNEL LINK chipset will normally require a single 100Ω resistor between the true and complement lines on
each differential pair of the receiver input. The actual value of the termination resistor should be selected to
match the differential mode characteristic impedance (90Ω to 120Ω typical) of the cable. Figure 22 shows an
example. No additional pull-up or pull-down resistors are necessary as with some other differential technologies
such as PECL. Surface mount resistors are recommended to avoid the additional inductance that accompanies
leaded resistors. These resistors should be placed as close as possible to the receiver input pins to reduce stubs
and effectively terminate the differential lines.
DECOUPLING CAPACITORS: Bypassing capacitors are needed to reduce the impact of switching noise which
could limit performance. For a conservative approach three parallel-connected decoupling capacitors (Multi-
Layered Ceramic type in surface mount form factor) between each V_CC and the ground plane(s) are
recommended. The three capacitor values are 0.1 μF, 0.01 μF and 0.001 μF. An example is shown in Figure 23.
The designer should employ wide traces for power and ground and ensure each capacitor has its own via to the
ground plane. If board space is limiting the number of bypass capacitors, the PLL V_CC should receive the most
filtering/bypassing. Next would be the LVDS V_CC pins and finally the logic V_CC pins.
Figure 22. LVDS Serialized Link Termination
Figure 23. CHANNEL LINK
Decoupling Configuration
14
Submit Documentation Feedback
Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: DS90CR287 DS90CR288A