DS90CR287MTDX Datasheet, PDF (11/24 Pages) Texas Instruments – DS90CR287/DS90CR288A +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link - 85MHz

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DS90CR287, DS90CR288A
SNLS056G – OCTOBER 1999 – REVISED MARCH 2013
Figure 20. Receiver LVDS Input Strobe Position
C—Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and
max
Tppos—Transmitter output pulse position (min and max)
RSKM ≥ Cable Skew (type, length) + Source Clock Jitter (cycle to cycle)⁽¹⁾ + ISI (Inter-symbol interference)⁽²⁾
Cable Skew—typically 10 ps–40 ps per foot, media dependent
(1) Cycle-to-cycle jitter is less than 150ps at 85MHz.
(2) ISI is dependent on interconnect length; may be zero.
Figure 21. Receiver LVDS Input Skew Margin
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