LM3S613 Datasheet, PDF (14/591 Pages) List of Unclassifed Manufacturers – Microcontroller

Table of Contents
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
Register 36:
Register 37:
Register 38:
Register 39:
Register 40:
Register 41:
Register 42:
Configuration and Control (CFGCTRL), offset 0xD14 ....................................................... 116
System Handler Priority 1 (SYSPRI1), offset 0xD18 ......................................................... 118
System Handler Priority 2 (SYSPRI2), offset 0xD1C ........................................................ 119
System Handler Priority 3 (SYSPRI3), offset 0xD20 ......................................................... 120
System Handler Control and State (SYSHNDCTRL), offset 0xD24 .................................... 121
Configurable Fault Status (FAULTSTAT), offset 0xD28 ..................................................... 125
Hard Fault Status (HFAULTSTAT), offset 0xD2C .............................................................. 131
Memory Management Fault Address (MMADDR), offset 0xD34 ........................................ 132
Bus Fault Address (FAULTADDR), offset 0xD38 .............................................................. 133
MPU Type (MPUTYPE), offset 0xD90 ............................................................................. 134
MPU Control (MPUCTRL), offset 0xD94 .......................................................................... 135
MPU Region Number (MPUNUMBER), offset 0xD98 ....................................................... 137
MPU Region Base Address (MPUBASE), offset 0xD9C ................................................... 138
MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4 ....................................... 138
MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC ...................................... 138
MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4 ....................................... 138
MPU Region Attribute and Size (MPUATTR), offset 0xDA0 ............................................... 140
MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8 .................................. 140
MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0 .................................. 140
MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8 .................................. 140
System Control ............................................................................................................................ 153
Register 1: Device Identification 0 (DID0), offset 0x000 ..................................................................... 165
Register 2: Power-On and Brown-Out Reset Control (PBORCTL), offset 0x030 .................................. 167
Register 3: LDO Power Control (LDOPCTL), offset 0x034 ................................................................. 168
Register 4: Raw Interrupt Status (RIS), offset 0x050 .......................................................................... 169
Register 5: Interrupt Mask Control (IMC), offset 0x054 ...................................................................... 170
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................. 171
Register 7: Reset Cause (RESC), offset 0x05C ................................................................................ 172
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 ......................................................... 173
Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 ............................................................. 177
Register 10: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 ........................................ 178
Register 11: Clock Verification Clear (CLKVCLR), offset 0x150 ............................................................ 179
Register 12: Allow Unregulated LDO to Reset the Part (LDOARST), offset 0x160 ................................. 180
Register 13: Device Identification 1 (DID1), offset 0x004 ..................................................................... 181
Register 14: Device Capabilities 0 (DC0), offset 0x008 ........................................................................ 183
Register 15: Device Capabilities 1 (DC1), offset 0x010 ........................................................................ 184
Register 16: Device Capabilities 2 (DC2), offset 0x014 ........................................................................ 186
Register 17: Device Capabilities 3 (DC3), offset 0x018 ........................................................................ 188
Register 18: Device Capabilities 4 (DC4), offset 0x01C ....................................................................... 190
Register 19: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 ................................... 191
Register 20: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 ................................. 193
Register 21: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ....................... 195
Register 22: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ................................... 197
Register 23: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 199
Register 24: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 201
Register 25: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 203
Register 26: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 204
Register 27: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 206
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July 14, 2014
Texas Instruments-Production Data