LM3S613 Datasheet, PDF (10/591 Pages) List of Unclassifed Manufacturers – Microcontroller

Table of Contents
Figure 12-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 417
Figure 12-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 418
Figure 13-1. I²C Block Diagram ............................................................................................. 447
Figure 13-2. I²C Bus Configuration ........................................................................................ 448
Figure 13-3. START and STOP Conditions ............................................................................. 448
Figure 13-4. Complete Data Transfer with a 7-Bit Address ....................................................... 449
Figure 13-5. R/S Bit in First Byte ............................................................................................ 449
Figure 13-6. Data Validity During Bit Transfer on the I²C Bus ................................................... 449
Figure 13-7. Master Single SEND .......................................................................................... 453
Figure 13-8. Master Single RECEIVE ..................................................................................... 454
Figure 13-9. Master Burst SEND ........................................................................................... 455
Figure 13-10. Master Burst RECEIVE ...................................................................................... 456
Figure 13-11. Master Burst RECEIVE after Burst SEND ............................................................ 457
Figure 13-12. Master Burst SEND after Burst RECEIVE ............................................................ 458
Figure 13-13. Slave Command Sequence ................................................................................ 459
Figure 14-1. Analog Comparator Module Block Diagram ......................................................... 483
Figure 14-2. Structure of Comparator Unit .............................................................................. 484
Figure 14-3. Comparator Internal Reference Structure ............................................................ 485
Figure 15-1. PWM Unit Diagram ............................................................................................ 496
Figure 15-2. PWM Module Block Diagram .............................................................................. 497
Figure 15-3. PWM Count-Down Mode .................................................................................... 498
Figure 15-4. PWM Count-Up/Down Mode .............................................................................. 499
Figure 15-5. PWM Generation Example In Count-Up/Down Mode ........................................... 499
Figure 15-6. PWM Dead-Band Generator ............................................................................... 500
Figure 16-1. 48-Pin QFP Package Pin Diagram ...................................................................... 533
Figure 19-1. Load Conditions ................................................................................................ 546
Figure 19-2. JTAG Test Clock Input Timing ............................................................................. 547
Figure 19-3. JTAG Test Access Port (TAP) Timing .................................................................. 548
Figure 19-4. JTAG TRST Timing ............................................................................................ 548
Figure 19-5. External Reset Timing (RST) .............................................................................. 549
Figure 19-6. Power-On Reset Timing ..................................................................................... 549
Figure 19-7. Brown-Out Reset Timing .................................................................................... 549
Figure 19-8. Software Reset Timing ....................................................................................... 550
Figure 19-9. Watchdog Reset Timing ..................................................................................... 550
Figure 19-10. LDO Reset Timing ............................................................................................. 550
Figure 19-11. ADC Input Equivalency Diagram ......................................................................... 552
Figure 19-12. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing
Measurement .................................................................................................... 553
Figure 19-13. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ................. 553
Figure 19-14. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ..................................... 554
Figure 19-15. I²C Timing ......................................................................................................... 555
Figure D-1. Stellaris LM3S613 48-Pin LQFP Package ........................................................... 582
Figure D-2. 48-Pin LQFP Tray Dimensions ........................................................................... 584
Figure D-3. 48-Pin LQFP Tape and Reel Dimensions ............................................................. 586
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July 14, 2014
Texas Instruments-Production Data