TMS320F28030_16 Datasheet, PDF (135/160 Pages) Texas Instruments – Piccolo Microcontrollers

TMS320F28030, TMS320F28031, TMS320F28032
TMS320F28033, TMS320F28034, TMS320F28035
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SPRS584K – APRIL 2009 – REVISED JUNE 2016
Table 6-65. Analog MUX for 56-Pin RSH and 64-Pin PAG Packages⁽¹⁾
AIOMUX1 REGISTER BITS
1-0
3-2
5-4
7-6
9-8
11-10
13-12
15-14
17-16
19-18
21-20
23-22
25-24
27-26
29-28
31-30
(1) I = Input, O = Output
AIOx AND PERIPHERAL SELECTION 1
AIOMUX1 BITS = 0,x
ADCINA0 (I), V_REFHI (I)
ADCINA1 (I)
AIO2 (I/O)
ADCINA3 (I)
AIO4 (I/O)
–
AIO6 (I/O)
ADCINA7 (I)
ADCINB0 (I)
ADCINB1 (I)
AIO10 (I/O)
ADCINB3 (I)
AIO12 (I/O)
–
AIO14 (I/O)
ADCINB7 (I)
DEFAULT AT RESET
PERIPHERAL SELECTION 2 AND
PERIPHERAL SELECTION 3
AIOMUX1 BITS = 1,x
ADCINA0 (I), V_REFHI (I)
ADCINA1 (I)
ADCINA2 (I), COMP1A (I)
ADCINA3 (I)
ADCINA4 (I), COMP2A (I)
–
ADCINA6 (I), COMP3A (I)
ADCINA7 (I)
ADCINB0 (I)
ADCINB1 (I)
ADCINB2 (I), COMP1B (I)
ADCINB3 (I)
ADCINB4 (I), COMP2B (I)
–
ADCINB6 (I), COMP3B (I)
ADCINB7 (I)
The user can select the type of input qualification for each GPIO pin via the GPxQSEL1/2 registers from
four choices:
• Synchronization To SYSCLKOUT Only (GPxQSEL1/2 = 0, 0): This is the default mode of all GPIO pins
at reset and it simply synchronizes the input signal to the system clock (SYSCLKOUT).
• Qualification Using Sampling Window (GPxQSEL1/2 = 0, 1 and 1, 0): In this mode the input signal,
after synchronization to the system clock (SYSCLKOUT), is qualified by a specified number of cycles
before the input is allowed to change.
• The sampling period is specified by the QUALPRD bits in the GPxCTRL register and is configurable in
groups of 8 signals. It specifies a multiple of SYSCLKOUT cycles for sampling the input signal. The
sampling window is either 3-samples or 6-samples wide and the output is only changed when ALL
samples are the same (all 0s or all 1s) as shown in Figure 4-18 (for 6 sample mode).
• No Synchronization (GPxQSEL1/2 = 1,1): This mode is used for peripherals where synchronization is
not required (synchronization is performed within the peripheral).
Due to the multilevel multiplexing that is required on the device, there may be cases where a peripheral
input signal can be mapped to more then one GPIO pin. Also, when an input signal is not selected, the
input signal will default to either a 0 or 1 state, depending on the peripheral.
Copyright © 2009–2016, Texas Instruments Incorporated
Detailed Description 135
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