TMS320F28030_16 Datasheet, PDF (101/160 Pages) Texas Instruments – Piccolo Microcontrollers

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TMS320F28030, TMS320F28031, TMS320F28032
TMS320F28033, TMS320F28034, TMS320F28035
SPRS584K – APRIL 2009 – REVISED JUNE 2016
6.9.4.2 SPI Slave Mode Electrical Data/Timing
Table 6-39 lists the slave mode external timing (clock phase = 0) and Table 6-40 (clock phase = 1).
Figure 6-31 and Figure 6-32 show the timing waveforms.
Table 6-39. SPI Slave Mode External Timing (Clock Phase = 0)^{(1)(2)(3)(4)(5)}
NO.
MIN
12 t_c(SPC)S
13 ^tw(SPCH)S
t_w(SPCL)S
14 ^tw(SPCL)S
t_w(SPCH)S
15 ^{td(SPCH-SOMI)S}
t_{d(SPCL-SOMI)S}
16 ^{tv(SPCL-SOMI)S}
t_{v(SPCH-SOMI)S}
19 ^{tsu(SIMO-SPCL)S}
t_{su(SIMO-SPCH)S}
20 ^{tv(SPCL-SIMO)S}
t_{v(SPCH-SIMO)S}
Cycle time, SPICLK
Pulse duration, SPICLK high (clock polarity = 0)
Pulse duration, SPICLK low (clock polarity = 1)
Pulse duration, SPICLK low (clock polarity = 0)
Pulse duration, SPICLK high (clock polarity = 1)
Delay time, SPICLK high to SPISOMI valid (clock polarity = 0)
Delay time, SPICLK low to SPISOMI valid (clock polarity = 1)
Valid time, SPISOMI data valid after SPICLK low (clock polarity = 0)
Valid time, SPISOMI data valid after SPICLK high (clock polarity = 1)
Setup time, SPISIMO before SPICLK low (clock polarity = 0)
Setup time, SPISIMO before SPICLK high (clock polarity = 1)
Valid time, SPISIMO data valid after SPICLK low (clock polarity = 0)
Valid time, SPISIMO data valid after SPICLK high (clock polarity = 1)
4t_c(LCO)
0.5t_c(SPC)S – 10
0.5t_c(SPC)S – 10
0.5t_c(SPC)S – 10
0.5t_c(SPC)S – 10
0
0
26
26
0.5t_c(SPC)S – 10
0.5t_c(SPC)S – 10
(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) t_c(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 15-MHz MAX, master mode receive 10-MHz MAX
Slave mode transmit 10-MHz MAX, slave mode receive 10-MHz MAX.
(4) t_c(LCO) = LSPCLK cycle time
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
MAX
0.5t_c(SPC)S
0.5t_c(SPC)S
0.5t_c(SPC)S
0.5t_c(SPC)S
21
21
UNIT
ns
ns
ns
ns
ns
ns
ns
SPICLK
(clock polarity = 0)
12
13
14
SPICLK
(clock polarity = 1)
15
16
SPISOMI
SPISOMI data Is valid
SPISIMO
19
20
SPISIMO data
must be valid
SPISTE^(A)
A. In the slave mode, the SPISTE signal should be asserted low at least 0.5t_c(SPC) (minimum) before the valid SPI clock
edge and remain low for at least 0.5t_c(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 6-31. SPI Slave Mode External Timing (Clock Phase = 0)
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Detailed Description 101
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