TMS320F28030_16 Datasheet, PDF (112/160 Pages) Texas Instruments – Piccolo Microcontrollers

TMS320F28030, TMS320F28031, TMS320F28032
TMS320F28033, TMS320F28034, TMS320F28035
SPRS584K – APRIL 2009 – REVISED JUNE 2016
www.ti.com
The CAN registers listed in Table 6-44 are used by the CPU to configure and control the CAN controller
and the message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM
can be accessed as 16 bits or 32 bits. 32-bit accesses are aligned to an even boundary.
Table 6-44. CAN Register Map⁽¹⁾
REGISTER NAME
eCAN-A
ADDRESS
SIZE (x32)
CANME
0x6000
1
CANMD
0x6002
1
CANTRS
0x6004
1
CANTRR
0x6006
1
CANTA
0x6008
1
CANAA
0x600A
1
CANRMP
0x600C
1
CANRML
0x600E
1
CANRFP
0x6010
1
CANGAM
0x6012
1
CANMC
0x6014
1
CANBTC
0x6016
1
CANES
0x6018
1
CANTEC
0x601A
1
CANREC
0x601C
1
CANGIF0
0x601E
1
CANGIM
0x6020
1
CANGIF1
0x6022
1
CANMIM
0x6024
1
CANMIL
0x6026
1
CANOPC
0x6028
1
CANTIOC
0x602A
1
CANRIOC
0x602C
1
CANTSC
0x602E
1
CANTOC
0x6030
1
CANTOS
0x6032
1
(1) These registers are mapped to Peripheral Frame 1.
DESCRIPTION
Mailbox enable
Mailbox direction
Transmit request set
Transmit request reset
Transmission acknowledge
Abort acknowledge
Receive message pending
Receive message lost
Remote frame pending
Global acceptance mask
Master control
Bit-timing configuration
Error and status
Transmit error counter
Receive error counter
Global interrupt flag 0
Global interrupt mask
Global interrupt flag 1
Mailbox interrupt mask
Mailbox interrupt level
Overwrite protection control
TX I/O control
RX I/O control
Time stamp counter (Reserved in SCC mode)
Time-out control (Reserved in SCC mode)
Time-out status (Reserved in SCC mode)
112 Detailed Description
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