TMS570LS1114_14 Datasheet, PDF (131/167 Pages) Texas Instruments – 16- and 32-Bit RISC Flash Microcontroller

TMS570LS1114
www.ti.com
SPNS188A – OCTOBER 2012 – REVISED SEPTEMBER 2013
Table 5-23. Dynamic Characteristics for the N2HET Input Capture Functionality
PARAMETER
MIN
1 Input signal period, PCNT or WCAP for rising edge (HRP) (LRP) tc_(VCLK2) + 2
to rising edge
2 Input signal period, PCNT or WCAP for falling edge (HRP) (LRP) tc_(VCLK2) + 2
to falling edge
3 Input signal high phase, PCNT or WCAP for rising 2 (HRP) tc_(VCLK2) + 2
edge to falling edge
4 Input signal low phase, PCNT or WCAP for falling 2 (HRP) tc_(VCLK2) + 2
edge to rising edge
MAX
2²⁵ (HRP) (LRP) tc_(VCLK2) - 2
2²⁵ (HRP) (LRP) tc_(VCLK2) - 2
2²⁵ (HRP) (LRP) tc_(VCLK2) - 2
2²⁵ (HRP) (LRP) tc_(VCLK2) - 2
UNIT
ns
ns
ns
ns
5.6.4 N2HET1-N2HET2 Synchronization
In some applications the N2HET resolutions must be synchronized. Some other applications require a
single time base to be used for all PWM outputs and input timing captures.
The N2HET provides such a synchronization mechanism. The Clk_master/slave (HETGCR.16) configures
the N2HET in master or slave mode (default is slave mode). A N2HET in master mode provides a signal
to synchronize the prescalers of the slave N2HET. The slave N2HET synchronizes its loop resolution to
the loop resolution signal sent by the master. The slave does not require this signal after it receives the
first synchronization signal. However, anytime the slave receives the re-synchronization signal from the
master, the slave must synchronize itself again..
N2HET1
EXT_LOOP_SYNC
NHET_LOOP_SYNC
N2HET2
NHET_LOOP_SYNC
EXT_LOOP_SYNC
Figure 5-11. N2HET1 – N2HET2 Synchronization Hookup
5.6.5 N2HET Checking
5.6.5.1 Internal Monitoring
To assure correctness of the high-end timer operation and output signals, the two N2HET modules can be
used to monitor each other’s signals as shown in Figure 5-12. The direction of the monitoring is controlled
by the I/O multiplexing control module.
N2HET1[1,3,5,7,9,11]
N2HET1
IOMM mux control signal x
N2HET1[1,3,5,7,9,11] / N2HET2[8,10,12,14,16,18]
N2HET2[8,10,12,14,16,18]
N2HET2
Figure 5-12. N2HET Monitoring
5.6.5.2 Output Monitoring using Dual Clock Comparator (DCC)
N2HET1[31] is connected as a clock source for counter 1 in DCC1. This allows the application to measure
the frequency of the pulse-width modulated (PWM) signal on N2HET1[31].
Copyright © 2012–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 131
Submit Documentation Feedback
Product Folder Links: TMS570LS1114