TMS570LS1114_14 Datasheet, PDF (1/167 Pages) Texas Instruments – 16- and 32-Bit RISC Flash Microcontroller

TMS570LS1114
www.ti.com
SPNS188A – OCTOBER 2012 – REVISED SEPTEMBER 2013
TMS570LS1114 16- and 32-Bit RISC Flash Microcontroller
Check for Samples: TMS570LS1114
1 TMS570LS1114 16- and 32-Bit RISC Flash Microcontroller
1.1 Features
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• High-Performance Automotive-Grade
Microcontroller for Safety-Critical Applications
– Dual CPUs Running in Lockstep
– ECC on Flash and RAM Interfaces
– Built-In Self-Test for CPU and On-chip RAMs
– Error Signaling Module with Error Pin
– Voltage and Clock Monitoring
• ARM® Cortex™ – R4F 32-Bit RISC CPU
– 1.66 DMIPS/MHz with 8-Stage Pipeline
– FPU with Single- and Double-Precision
– 12-Region Memory Protection Unit
– Open Architecture with Third-Party Support
• Operating Conditions
– Up to 180-MHz System Clock
– Core Supply Voltage (VCC): 1.14 to 1.32 V
– I/O Supply Voltage (VCCIO): 3.0 to 3.6 V
• Integrated Memory
– 1MB of Program Flash with ECC
– 128KB of RAM with ECC
– 64KB of Flash for Emulated EEPROM with
ECC
• 16-Bit External Memory Interface (EMIF)
• Common Platform Architecture
– Consistent Memory Map Across Family
– Real-Time Interrupt (RTI) Timer (OS Timer)
– 128-Channel Vectored Interrupt Module (VIM)
– 2-Channel Cyclic Redundancy Checker
(CRC)
• Direct Memory Access (DMA) Controller
– 16 Channels and 32 Control Packets
– Parity Protection for Control Packet RAM
– DMA Accesses Protected by Dedicated MPU
• Frequency-Modulated Phase-Locked Loop
(FMPLL) with Built-In Slip Detector
• Separate Nonmodulating PLL
• IEEE 1149.1 JTAG, Boundary Scan and ARM
CoreSight™ Components
• Advanced JTAG Security Module (AJSM)
• Trace and Calibration Capabilities
– Parameter Overlay Module (POM)
• Sixteen General-Purpose Input/Output (GPIO)
Pins Capable of Generating Interrupts
• Enhanced Timing Peripherals for Motor Control
– 7 Enhanced Pulse Width Modulator (ePWM)
Modules
– 6 Enhanced Capture (eCAP) Modules
– 2 Enhanced Quadrature Encoder Pulse
(eQEP) Modules
• Two High-End Timer (N2HETs) Modules
– N2HET1: 32 Programmable Channels
– N2HET2: 18 Programmable Channels
– 160-Word Instruction RAM with Parity
Protection Each
– Each N2HET Includes Hardware Angle
Generator
– Dedicated Transfer Units (HTU) on N2HETs
• Two 10- and 12-Bit Multibuffered Analog-to-
Digital Converter (MibADC) Modules
– ADC1: 24 Channels
– ADC2: 16 Channels Shared with ADC1
– 64 Result Buffers with Parity Protection Each
• Multiple Communication Interfaces
– Three CAN Controllers (DCANs)
• 64 Mailboxes with Parity Protection Each
• Compliant to CAN Protocol Version 2.0A
and 2.0B
– Inter-Integrated Circuit (I²C)
– Three Multibuffered Serial Peripheral
Interface (MibSPI) Modules
• 128 Words with Parity Protection Each
• 8 Transfer Groups
– Up to Two Standard Serial Peripheral
Interface (SPI) Modules
– Two UART (SCI) Interfaces, One with Local
Interconnect Network (LIN 2.1) Interface
Support
• Packages
– 144-Pin Quad Flatpack (PGE) [Green]
– 337-Ball Grid Array (ZWT) [Green]
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