DS92LV1212_11 Datasheet, PDF (12/15 Pages) Texas Instruments – 16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer with Embedded Clock Recovery

Application Information (Continued)
and lowers threshold margin at the Deserializers. Deserial-
izer devices should be placed no more than 1 inch from the
slot connector.
Transmission Media
The Serializer and Deserializer are designed for data trans-
mission over a multi-drop bus. Multi-drop buses use a single
Serializer and multiple Deserializer devices. Since the Seri-
alizer can be driving from any point on the bus, the bus must
be terminated at both ends. For example, a 100 Ohm differ-
ential bus must be terminated at each end with 100 Ohms
lowering the DC impedance that the Serializer must drive to
50 Ohms. This load is further lowered by the addition of mul-
tiple Deserializers. Adding up to 20 Deserializers to the bus
(depending upon spacing) will lower the total load to about
27 Ohms (54 Ohm bus). The Serializer is designed for DC
loads between 27 and 100 Ohms.
The Serializer and Deserializer can also be used in
point-to-point configuration of a backplane, PCB trace or
through a twisted pair cable. In point-to-point configurations
the transmission media need only be terminated at the re-
ceiver end. In the point-to-point configuration the potential of
offsetting the ground levels of the Serializer vs. the Deserial-
izer must be considered. Bus LVDS provides a plus / minus
one volt common mode range at the receiver inputs.
DS100982-26
The DS92LV1212 can be “Hot Inserted” into operating serial busses without interrupting bus communication. The random lock feature allows the DS92LV1212
to synchronize to the bus traffic and receive data.
FIGURE 10. Random Lock Allows Hot Insertion into Serial Busses
Pin Diagram
DS92LV1212TMSA - Deserializer
Deserializer Pin Description
Pin Name
ROUT
I/O
No.
O
15–19,
24–28
DS100982-19
Description
Data Output. ±9 mA CMOS level outputs.
11
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