LMH0395 Datasheet, PDF (11/21 Pages) Texas Instruments – 3G HD/SD SDI Dual Output Low Power Extended Reach Adaptive Cable Equalizer

shifted out on the MISO output during the first 16-bit transac-
tion, and are typically ignored (this is shown as “Don't Care”
on the MISO output in Figure 3. SS must return high and then
is driven low again before the second 16 bits (all “1”s) are sent
to the LMH0395's MOSI input. Once again, the prior SPI com-
mand, address, and data are shifted out on the MISO output,
but this data now includes the requested read data. The read
data is available on the MISO output during the second 8 bits
of the 16-bit dummy read transaction, as shown by D7-D0 in
Figure 3.
SPI Daisy-Chain Operation
The LMH0395 SPI controller supports daisy-chaining the se-
rial data between an unlimited number of LMH0395 devices.
Each LMH0395 device is directly connected to the SCK and
SS pins on the host. However, only the first LMH0395 device
in the chain is connected to the host’s MOSI pin, and only the
last device in the chain is connected to the host’s MISO pin.
The MISO pin of each intermediate LMH0395 device in the
chain is connected to the MOSI pin of the next LMH0395 de-
vice, creating a serial shift register. This daisy-chain architec-
ture is shown in Figure 7.
FIGURE 7. SPI Daisy Chain System Architecture
30115720
In a daisy-chain configuration of N LMH0395 devices, the host
conceptually sees a shift register of length 16xN. Therefore
the length of SPI transactions (as previously described) is
16xN bits, and SS must be asserted for 16xN clock cycles for
each SPI transaction.
SPI Daisy-Chain Write
Figure 8 shows the SPI daisy-chain write for a daisy-chain of
N devices. The SS signal is driven low and SCK is toggled for
16xN clocks. The 16xN bit MOSI payload (sent to Device 1 in
the daisy-chain) consists of the 16-bit SPI write data for De-
vice N (the last device in the chain), followed by the write data
for Device N-1, Device N-2, etc., ending with the write data
for Device 1 (the first device in the chain). The 16-bit SPI write
data for each device consists of a “0” (write command), seven
address bits, and eight data bits. After the SPI daisy-chain
write, SS must return high and then the write occurs for all
devices in the daisy-chain.
FIGURE 8. SPI Daisy-Chain Write
11
30115725
www.ti.com