LMH0395 Datasheet, PDF (10/21 Pages) Texas Instruments – 3G HD/SD SDI Dual Output Low Power Extended Reach Adaptive Cable Equalizer

FIGURE 5. DC Output Interface to LMH0346 Reclocker
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FIGURE 6. DC Output Interface to LMH0356 Reclocker
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SPI Register Access
Setting SPI_EN high enables the optional SPI register access
mode. In SPI mode, the LMH0395 provides register access
to all of its features along with a cable length indicator, pro-
grammable output de-emphasis, programmable output com-
mon mode voltage and swing, digital MUTE_REF, and launch
amplitude optimization. There are eight supported 8-bit reg-
isters in the device (see Table 1). The LMH0395 supports SPI
daisy-chaining among an unlimited number of LMH0395 de-
vices.
SPI Transaction Overview
Each SPI transaction to a single device is 16-bits long. The
transaction is initiated by driving SS low, and completed by
returning SS high. The 16-bit MOSI payload consists of the
read/write command (“1” for reads and “0” for writes), the
seven address bits of the device register (MSB first), and the
eight data bits (MSB first). The LMH0395 MOSI input data is
latched on the rising edge of SCK, and the MISO output data
is sourced on the falling edge of SCK.
In order to facilitate daisy-chaining, the prior SPI command,
address, and data are shifted out on the MISO output as the
current command, address, and data are shifted in on the
MOSI input. For SPI writes, the MISO output is typically ig-
nored as “Don't Care” data. For SPI reads, the MISO output
provides the requested read data (after 16 periods of SCK).
The MISO output is active when SS low, and tri-stated when
SS is high.
SPI Write
The SPI write is shown in Figure 2. The SPI write is 16 bits
long. The 16-bit MOSI payload consists of a “0” (write com-
mand), seven address bits, and eight data bits. The SS signal
is driven low, and the 16 bits are sent to the LMH0395's MOSI
input. After the SPI write, SS must return high. The prior SPI
command, address, and data shifted out on the MISO output
during the SPI write is shown as “Don't Care” on the MISO
output in Figure 2.
SPI Read
The SPI read is shown in Figure 3. The SPI read is 32 bits
long, consisting of a 16-bit read transaction followed by a 16-
bit dummy read transaction to shift out the read data on the
MISO output. The first 16-bit MOSI payload consists of a
“1” (read command), seven address bits, and eight “1”s which
are ignored. The second 16-bit MOSI payload consists of 16
“1”s which are ignored but necessary in order to shift out the
requested read data on the MISO output. The SS signal is
driven low, and the first 16 bits are sent to the LMH0395's
MOSI input. The prior SPI command, address, and data are
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