LMH6702QML_17 Datasheet, PDF (10/17 Pages) Texas Instruments – 1.7 GHz, Ultra Low Distortion, Wideband Op Amp

LMH6702QML
SNOSAQ2E – JULY 2005 – REVISED MARCH 2013
www.ti.com
In applications where the LMH6702 is replacing the CLC409, care must be taken when the device is lightly
loaded and some capacitance is present at the output. Due to the much higher frequency response of the
LMH6702 compared to the CLC409, there could be increased susceptibility to low value output capacitance
(parasitic or inherent to the board layout or otherwise being part of the output load). As already mentioned, this
susceptibility is most noticeable when the LMH6702's resistive load is light. Parasitic capacitance can be
minimized by careful lay out. Addition of an output snubber R-C network will also help by increasing the high
frequency resistive loading.
Referring back to Figure 24, it must be noted that several additional constraints should be considered in driving
the capacitive input of an ADC. There is an option to increase R_S, band-limiting at the ADC input for either noise
or Nyquist band-limiting purposes. Increasing R_S too much, however, can induce an unacceptably large input
glitch due to switching transients coupling through from the "convert" signal. Also, C_IN is oftentimes a voltage
dependent capacitance. This input impedance non-linearity will induce distortion terms that will increase as R_S is
increased. Only slight adjustments up or down from the recommended R_S value should therefore be attempted in
optimizing system performance.
DC ACCURACY AND NOISE
Example below shows the output offset computation equation for the non-inverting configuration using the typical
bias current and offset specifications for A_V = + 2:
Output Offset : V_O = (±I_BN · R_IN ± V_IO) (1 + R_F/R_G) ± I_BI · R_F
Where R_IN is the equivalent input impedance on the non-inverting input.
Example computation for A_V = +2, R_F = 237Ω, R_IN = 25Ω:
V_O = (±6μA · 25Ω ± 1mV) (1 + 237/237) ± 8μA · 237 = ±4.20mV
A good design, however, should include a worst case calculation using Min/Max numbers in the data sheet
tables, in order to ensure "worst case" operation.
Further improvement in the output offset voltage and drift is possible using the composite amplifiers described in
Application Note OA-7 SNOA365. The two input bias currents are physically unrelated in both magnitude and
polarity for the current feedback topology. It is not possible, therefore, to cancel their effects by matching the
source impedance for the two inputs (as is commonly done for matched input bias current devices).
The total output noise is computed in a similar fashion to the output offset voltage. Using the input noise voltage
and the two input noise currents, the output noise is developed through the same gain equations for each term
but combined as the square root of the sum of squared contributing elements. See Application Note OA-12
SNOA375 for a full discussion of noise calculations for current feedback amplifiers.
PRINTED CIRCUIT LAYOUT
Generally, a good high frequency layout will keep power supply and ground traces away from the inverting input
and output pins. Parasitic capacitances on these nodes to ground will cause frequency response peaking and
possible circuit oscillations (see Application Note OA-15 SNOA367 for more information). Texas Instruments
suggests the following evaluation boards as a guide for high frequency layout and as an aid in device testing and
characterization:
Device
LMH6702QMLMF
LMH6702QMLMA
Package
SOT-23-5
Plastic SOIC
Evaluation Board Part Number
CLC730216
CLC730227
10
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