TMS320VC5504 Datasheet, PDF (97/128 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

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6.12.2 I2C Electrical Data/Timing
TMS320VC5504
Fixed-Point Digital Signal Processor
SPRS609A – JUNE 2009 – REVISED JULY 2009
Table 6-21. Timing Requirements for I2C Timings⁽¹⁾ (see Figure 6-22)
CV_DD = 1.05 V
CV_DD = 1.3 V
NO.
STANDARD
MODE
FAST MODE
UNIT
MIN MAX
MIN MAX
1
t_c(SCL)
Cycle time, SCL
10
2
t_{su(SCLH-SDAL)}
Setup time, SCL high before SDA low (for a repeated START
condition)
4.7
2.5
µs
0.6
µs
3
t_h(SCLL-SDAL)
Hold time, SCL low after SDA low (for a START and a repeated
START condition)
4
0.6
µs
4
t_w(SCLL)
Pulse duration, SCL low
5
t_w(SCLH)
Pulse duration, SCL high
6 t_{su(SDAV-SCLH)} Setup time, SDA valid before SCL high
7
t_h(SDA-SCLL)
Hold time, SDA valid after SCL low
8
t_w(SDAH)
Pulse duration, SDA high between STOP and START
conditions
9
t_r(SDA)
10
t_r(SCL)
11
t_f(SDA)
12
t_f(SCL)
Rise time, SDA⁽⁵⁾
Rise time, SCL⁽⁵⁾
Fall time, SDA⁽⁵⁾
Fall time, SCL⁽⁵⁾
13 t_{su(SCLH-SDAH)} Setup time, SCL high before SDA high (for STOP condition)
14 t_w(SP)
15
C_b ⁽⁶⁾
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
4.7
1.3
µs
4
0.6
µs
250
100 ⁽²⁾
ns
0 ⁽³⁾
0⁽³⁾ 0.9 ⁽⁴⁾ µs
4.7
1.3
1000
1000
300
300
20 + 0.1C_b(6)
20 + 0.1C_b(6)
20 + 0.1C_b(6)
20 + 0.1C_b(6)
4
0.6
0
400
µs
300 ns
300 ns
300 ns
300 ns
µs
50 ns
400 pF
(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down. Also these pins are not 3.6 V-tolerant (their V_IH cannot go above DV_DDIO + 0.3 V).
(2) A Fast-mode I²C-bus™ device can be used in a Standard-mode I²C-bus system, but the requirement t_su(SDA-SCLH)≥ 250 ns must then be
met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line t_r max + t_su(SDA-SCLH)= 1000 + 250 = 1250 ns
(according to the Standard-mode I²C-Bus Specification) before the SCL line is released.
(3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V_IHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
(4) The maximum t_h(SDA-SCLL) has only to be met if the device does not stretch the low period [t_w(SCLL)] of the SCL signal.
(5) The rise/fall times are measured at 30% and 70% of DV_DDIO. The fall time is only slightly influenced by the external bus load (C_b) and
external pullup resistor. However, the rise time (t_r) is mainly determined by the bus load capacitance and the value of the pullup resistor.
The pullup resistor must be selected to meet the I2C rise and fall time values specified.
(6) C_b = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
SDA
SCL
11
8
4
10
6
5
Stop
Start
1
3
12
3
7
2
Repeated
Start
Figure 6-22. I2C Receive Timings
9
14
13
Stop
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