TMS320VC5504 Datasheet, PDF (14/128 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

TMS320VC5504
Fixed-Point Digital Signal Processor
SPRS609A – JUNE 2009 – REVISED JULY 2009
Table 3-3. SARAM Blocks (continued)
CPU
BYTE ADDRESS RANGE
034000h – 035FFFh
036000h – 037FFFh
038000h – 039FFFh
03A000h – 03BFFFh
03C000h – 03DFFFh
03E000h – 03FFFFh
040000h – 04FFFFh
DMA/USB CONTROLLER
BYTE ADDRESS RANGE
000B 4000h – 000B 5FFFh
000B 6000h – 000B 7FFFh
000B 8000h – 000B 9FFFh
000B A000h – 000B BFFFh
000B C000h – 000B DFFFh
000B E000h – 000B FFFFh
000C 0000h – 000C FFFFh
MEMORY BLOCK
SARAM 18
SARAM 19
SARAM 20
SARAM 21
SARAM 22
SARAM 23
Reserved
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3.2.3 On-Chip Read-Only Memory (ROM)
The zero-wait-state ROM is located at the byte address range FE0000h – FFFFFFh. The ROM is
composed of four 16K-word blocks, for a total of 128K bytes of ROM. The ROM address space can be
mapped by software to the external memory or to the internal ROM.
The standard VC5504 device includes a Bootloader program resident in the ROM.
When the MPNMC bit field of the ST3 status register is cleared (by default), the byte address range
FE0000h – FFFFFFh is reserved for the on-chip ROM. When the MPNMC bit field of the ST3 status
register is set through software, the on-chip ROM is disabled and not present in the memory map, and
byte address range FE0000h – FFFFFFh is directed to external memory space. A hardware reset always
clears the MPNMC bit, so it is not possible to disable the ROM at reset. However, the software reset
instruction does not affect the MPNMC bit. The ROM can be accessed by the program and data buses.
Each on-chip ROM block is a one cycle per word access memory.
3.2.4 External Memory
The external memory space of the device is located at the byte address range 050000h – FFFFFFh. The
external memory space is divided into four chip select spaces: EMIF CS2 through CS5 space dedicated to
asynchronous devices including flash. Each chip select space has a corresponding chip select pin (called
EMIF_CSx) that is activated during an access to the chip select space.
The external memory interface (EMIF) provides the means for the DSP to access external memories and
other devices including: NOR Flash, NAND Flash, and SRAM. Before accessing external memory, you
must configure the EMIF through its memory-mapped registers.
The EMIF provides a configurable 16- or 8-bit data bus, an address bus width of up to 21-bits, and 4
dedicated chip selects, along with memory control signals. To maximize power savings, the I/O pin of the
EMIF can be operated at an independent voltage from the rest of other I/O pins on the device.
For more details on the EMIF, see the TMS320VC5505 Digital Signal Processor (DSP) External Memory
Interface (EMIF) User’s Guide (literature number SPRUFO8).
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Device Overview
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