TMS320VC5504 Datasheet, PDF (55/128 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

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TMS320VC5504
Fixed-Point Digital Signal Processor
SPRS609A – JUNE 2009 – REVISED JULY 2009
4.7.1.2 MMC1, I2S1, and GP[11:6] Pin Multiplexing [EBSR.SP1MODE Bits]
The MMC1, I2S1, and GPIO signal muxing is determined by the value of the SP1MODE bit fields in the
External Bus Selection Register (EBSR) register. For more details on the actual pin functions, see .
Table 4-5. MMC1, I2S1, and GP[11:6] Pin Multiplexing
PDINHIBR1
REGISTER
BIT FIELDS⁽¹⁾
PIN MUX
SIGNAL NAME
MODE 0
00
EBSR SP1MODE BITS
MODE 1
01
MODE 2
10
S10PD
MMC1_CLK/I2S1_CLK/GP[6]
MMC1_CLK
I2S1_CLK
GP[6]
S11PD
MMC1_CMD/I2S1_FS/GP[7]
MMC1_CMD
I2S1_FS
GP[7]
S12PD
MMC1_D0/I2S1_DX/GP[8]
MMC1_D0
I2S1_DX
GP[8]
S13PD
MMC1_D1/I2S1_RX/GP[9]
MMC1_D1
I2S1_RX
GP[9]
S14PD
MMC1_D2/GP[10]
MMC1_D2
GP[10]
GP[10]
S15PD
MMC1_D3/GP[11]
MMC1_D3
GP[11]
GP[11]
(1) The pin mux signals names with PDINHIBR1 register bit field references can have the pulldown register enabled or disabled via this
register.
4.7.1.3 MMC0, I2S0, and GP[5:0] Pin Multiplexing [EBSR.SP0MODE Bits]
The MMC0, I2S0, and GPIO signal muxing is determined by the value of the SP0MODE bit fields in the
External Bus Selection Register (EBSR) register. For more details on the actual pin functions, see
Table 4-6.
Table 4-6. MMC0, I2S0, and GP[5:0] Pin Multiplexing
PDINHIBR1
REGISTER
BIT FIELDS⁽¹⁾
PIN MUX
SIGNAL NAME
MODE 0
00
EBSR SP0MODE BITS
MODE 1
01
MODE 2
10
S00PD
MMC0_CLK/I2S0_CLK/GP[0]
MMC0_CLK
I2S0_CLK
GP[0]
S01PD
MMC0_CMD/I2S0_FS/GP[1]
MMC0_CMD
I2S0_FS
GP[1]
S02PD
MMC0_D0/I2S0_DX/GP[2]
MMC0_D0
I2S0_DX
GP[2]
S03PD
MMC0_D1/I2S0_RX/GP[3]
MMC0_D1
I2S0_RX
GP[3]
S04PD
MMC0_D2/GP[4]
MMC0_D2
GP[4]
GP[4]
S05PD
MMC0_D3/GP[5]
MMC0_D3
GP[5]
GP[5]
(1) The pin mux signals names with PDINHIBR1 register bit field references can have the pulldown register enabled or disabled via this
register.
4.7.1.4 EMIF EM_A[20:15] and GP[26:21] Pin Multiplexing [EBSR.Axx_MODE bits]
The EMIF Address and GPIO signal muxing is determined by the value of the A20_MODE, A19_MODE,
A18_MODE, A17_MODE, A16_MODE, and A15_MODE bit fields in the External Bus Selection Register
(EBSR) register. For more details on the actual pin functions, see Table 4-7.
EM_A[15]/GP[21]
EM_A[16]/GP[22]
EM_A[17]/GP[23]
EM_A[18]/GP[24]
EM_A[19]/GP[25]
EM_A[20]/GP[26]
Table 4-7. EM_A[20:16] and GP[26:21] Pin Multiplexing
PIN MUX
SIGNAL NAME
0
EM_A[15]
EM_A[16]
EM_A[17]
EM_A[18]
EM_A[19]
EM_A[20]
Axx_MODE BIT
1
GP[21]
GP[22]
GP[23]
GP[24]
GP[25]
GP[26]
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