TMS320VC5504 Datasheet, PDF (108/128 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

TMS320VC5504
Fixed-Point Digital Signal Processor
SPRS609A – JUNE 2009 – REVISED JULY 2009
6.15.2 SPI Electrical Data/Timing
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Table 6-35. Timing Requirements for SPI input (see Figure 6-26 through Figure 6-29)
NO.
5
t_C(SCLK)
Cycle time, SPI_CLK
6
t_w(SCLKH)
7
t_w(SCLKL)
Pulse duration, SPI_CLK high
Pulse duration, SPI_CLK low
Setup time, SPI_RX valid before SPI_CLK high, SPI Mode 0
Setup time, SPI_RX valid before SPI_CLK low, SPI Mode 1
8 t_{su(SRXV-SCLK) Setup time, SPI_RX valid before SPI_CLK high, SPI Mode 2}
Setup time, SPI_RX valid before SPI_CLK high, SPI Mode 3
Hold time, SPI_RX vaild after SPI_CLK high, SPI Mode 0
Hold time, SPI_RX vaild after SPI_CLK low, SPI Mode 1
9 t_{h(SCLK-SRXV) Hold time, SPI_RX vaild after SPI_CLK low, SPI Mode 2}
Hold time, SPI_RX vaild after SPI_CLK high, SPI Mode 3
CV_DD = 1.05 V
MIN
MAX
66.4 or
4P ^{(1) (2)}
30
30
15
15
15
15
0
0
0
0
CV_DD = 1.3 V
MIN
MAX
40 or
4P^{(1) (2)}
19
19
13
13
13
13
0
0
0
0
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1) P = SYSCLK period in ns. For example, when running parts at 100 MHz, use P = 10 ns.
(2) Use whichever value is greater.
Table 6-36. Switching Characteristics Over Recommended Operating Conditions for SPI Outputs
(see Figure 6-26 through Figure 6-29)
NO.
1 t_d(SCLK-STXV)
2 t_{oh(SCLK-STXIV)}
3 t_{d(SPICS-SCLK)}
4 t_{oh(SCLKI-SPICSI)}
PARAMETER
Delay time, SPI_CLK low to SPI_TX vaild, SPI
Mode 0
Delay time, SPI_CLK high to SPI_TX vaild, SPI
Mode 1
Delay time, SPI_CLK high to SPI_TX vaild, SPI
Mode 2
Delay time, SPI_CLK low to SPI_TX vaild, SPI
Mode 3
Output hold time, SPI_CLK high to SPI_TX invaild,
SPI Mode 0
Output hold time, SPI_CLK low to SPI_TX invaild,
SPI Mode 1
Output hold time, SPI_CLK low to SPI_TX invaild,
SPI Mode 2
Output hold time, SPI_CLK high to SPI_TX invaild,
SPI Mode 3
Delay time, SPI_CS active to SPI_CLK active
Output hold time, SPI_CS inactive to SPI_CLK
inactive
CV_DD = 1.05 V
MIN
MAX
8
8
8
8
t_w(SCLKH) - 4
t_w(SCLKL) - 4
t_w(SCLKL) - 4
t_w(SCLKH) - 4
t_C - 8 + D⁽¹⁾
0.5t_C - 2
CV_DD = 1.3 V
UNIT
MIN
MAX
5 ns
5 ns
5 ns
5 ns
t_w(SCLKH) -
4.5
ns
t_w(SCLKL) -
4.5
ns
t_w(SCLKL) -
4.5
ns
t_w(SCLKH) -
4.5
ns
t_C - 8 + D⁽¹⁾ ns
0.5t_C - 2
ns
(1) D is the programable data delay in ns. Data delay can be programmed to 0, 1, 2, or 3 SPICLK clock cycles.
108 Peripheral Information and Electrical Specifications
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