DAC39J84_15 Datasheet, PDF (96/146 Pages) Texas Instruments – DAC39J84 Quad-Channel, 16-Bit, 2.8 GSPS, Digital-to-Analog Converter with 12.5 Gbps JESD204B Interface

DAC39J84
SLASE48A – NOVEMBER 2014 – REVISED JANUARY 2015
7.5.1.60 config59 Register – Address: 0x3B, Default: 0x0000
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15
serdes_ clk_sel
7
Register
Name
config59
Addr
(Hex)
0x3B
Figure 141. config59 Register Format
14
13
12
11
10
9
8
serdes_ refclk_div
reserved
6
5
4
3
2
1
0
reserved
reserved
Table 90. config59 Register Field Descriptions
Bit Name
15 serdes_ clk_sel
14:11
10:2
1:0
serdes_
refclk_div
reserved
reserved
Function
Select either the DAC PLL output or the DACCLK from the pins to be
the SerDes PLL reference divider input clock.
The divide amount for the serdes PLL reference clock divider. The
divider amount is serdes_refclk_div plus one.
Reserved
Reserved
Default
Value
0
0000
000000000
00
7.5.1.61 config60 Register – Address: 0x3C, Default: 0x0000
Figure 142. config60 Register Format
15
14
13
12
11
10
9
8
rw_cfgpll
7
6
5
4
3
2
1
0
rw_cfgpll
Register
Name
config60
Addr
(Hex)
0x3C
Table 91. config60 Register Field Descriptions
Bit Name
Function
15:0 rw_cfgpll Control the PLL of the SerDes.
Bit15 – ENDIVCLK, enables output of a divide-by-5 of PLL clock.
Bit14:13 – reserved.
Bit12:11 – LB, specify loop bandwidth settings.
Bit10 – SLEEPPLL, puts the PLL into sleep state when high.
Bit9
– VRANGE, select between high and low VCO.
Bit8:1 – MPY, select PLL multiply factor between 4 and 25.
Bit0
– reserved.
Default
Value
0x0000
96
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