DAC39J84_15 Datasheet, PDF (29/146 Pages) Texas Instruments – DAC39J84 Quad-Channel, 16-Bit, 2.8 GSPS, Digital-to-Analog Converter with 12.5 Gbps JESD204B Interface

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DAC39J84
SLASE48A – NOVEMBER 2014 – REVISED JANUARY 2015
Table 2. Lane Rate Selection
RATE
EFFECT
00 Full rate. Four data samples taken per SerDes PLL output clock cycle.
01 Half rate. Two data samples taken per SerDes PLL output clock cycle..
10 Quarter rate. One data samples taken per SerDes PLL output clock cycle.
11 Eighth rate. One data samples taken every two SerDes PLL output clock cycles.
7.3.3 Serdes PLL
DAC39J84 has two integrated PLLs, one PLL is to provide the clocking of DAC, which will be discussed in a
DAC PLL section; the other PLL is to provide the clocking for the high speed SerDes. The reference frequency of
the SerDes PLL can be in the range of 100-800MHz nominal, and 300-800MHz optimal.
The reference frequency is derived from DACCLK divided down based on the serdes_refclk_div programming,
as shown in Figure 56.
External Loop
Filter
DAC PLL
DACCLKP
DACCLKN
N
Divider
PFD &
CP
Internal Loop
VCO
Filter
M
Divider
Prescaler
DACCLK
0
Divider
REFCLK for
SerDes PLL
1
mem_serdes_refclk_sel
mem_serdes_refclk_div
Figure 56. Reference Clock of SerDes PLL
During normal operation, the clock generated by PLL will be 4-25 times the reference frequency, according to the
multiply factor selected via rw_cfgpll [8:1] (MPY). In order to select the appropriate multiply factor and refclkp/n
frequency, it is first necessary to determine the required PLL output clock frequency. The relationship between
the PLL output clock frequency and the lane rate is shown in Table 3. Having computed the PLL output
frequency, the reference frequency can be obtained by dividing this by the multiply factor specified via MPY.
NOTE
High multiplication factor settings will be especially sensitive to reference clock jitter and
should not be employed without prior consultation with TI.
Table 3. Relationship Between Lane Rate and SerDes PLL Output Frequency
RATE
Full
Half
LINE RATE
x Gbps
x Gbps
PLL OUTPUT FREQUENCY
0.25x GHz
0.5x GHz
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