DAC39J84_15 Datasheet, PDF (1/146 Pages) Texas Instruments – DAC39J84 Quad-Channel, 16-Bit, 2.8 GSPS, Digital-to-Analog Converter with 12.5 Gbps JESD204B Interface

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DAC39J84
SLASE48A – NOVEMBER 2014 – REVISED JANUARY 2015
DAC39J84 Quad-Channel, 16-Bit, 2.8 GSPS, Digital-to-Analog Converter
with 12.5 Gbps JESD204B Interface
1 Features
•1 Resolution: 16-Bit
• Maximum Sample Rate: 2.8GSPS
• Maximum Input Data Rate: 1.25GSPS
• JESD204B Interface
– 8 JESD204B Serial Input Lanes
– 12.5 Gbps Maximum Bit Rate per Lane
– Subclass 1 Multi-DAC Synchronization
• On-Chip Very Low Jitter PLL
• Selectable 1x -16x Interpolation
• Independent Complex Mixers with 48-bit NCO/ or
±n×Fs/8
• Wideband Digital Quadrature Modulator
Correction
• Sinx/x Correction Filters
• Fractional Sample Group Delay Correction
• Multi-Band Mode: Digital Summation of
Independent Complex Signals
• 3/4-Wire Serial Control Bus (SPI)
• Integrated Temperature Sensor
• JTAG Boundary Scan
• Pin-Compatible with Quad-Channel
DAC37J84/DAC38J84 Family
• Power Dissipation: 1.8W at 2.8GSPS
• Package: 10 mm x 10 mm, 144-Ball Flip-Chip
BGA
2 Applications
• Cellular Base Stations
• Diversity Transmit
• Wideband Communications
• Direct Digital Synthesis (DDS) instruments
• Defense/Military
• Millimeter/Microwave Backhaul
• Automated Test Equipment
• Cable Infrastructure
3 Description
The DAC39J84 is a low power, 16-bit, quad-channel,
2.8 GSPS digital to analog converter (DAC) with
JESD204B interface.
Digital data is input to the device through 1, 2, 4 or 8
configurable serial JESD204B lanes running up to
12.5 Gbps with on-chip termination and
programmable equalization. The interface allows
JESD204B Subclass 1 SYSREF based deterministic
latency and full synchronization of multiple devices.
The device includes features that simplify the design
of complex transmit architectures. Fully bypassable
2x to 16x digital interpolation filters with over 90 dB of
stop-band attenuation simplify the data interface and
reconstruction filters. An on-chip 48-bit Numerically
Controlled Oscillator (NCO) and independent
complex mixers allow flexible and accurate carrier
placement.
A high-performance low jitter PLL simplifies clocking
of the device without significant impact on the
dynamic range. The digital Quadrature Modulator
Correction (QMC) and Group Delay Correction (QDC)
enable complete IQ compensation for gain, offset,
phase, and group delay between channels in direct
up-conversion applications. A programmable Power
Amplifier (PA) protection mechanism is available to
provide PA protection in cases when the abnormal
power behavior of the input data is detected.
Device Information⁽¹⁾
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DAC39J84
FCBGA (144)
10.00 mm x 10.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
DAC39J84
16-bit DAC
xN
RF
16-bit DAC
xN
16-bit DAC
xN
RF
16-bit DAC
xN
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.