DAC39J84_15 Datasheet, PDF (91/146 Pages) Texas Instruments – DAC39J84 Quad-Channel, 16-Bit, 2.8 GSPS, Digital-to-Analog Converter with 12.5 Gbps JESD204B Interface

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7.5.1.48 config47 Register – Address: 0x2F, Default: 0x0004
DAC39J84
SLASE48A – NOVEMBER 2014 – REVISED JANUARY 2015
Figure 129. config47 Register Format
15
14
13
12
reserved
titest_dieid_rea
d_ena
reserved
7
6
5
4
reserved
11
10
9
8
reserved
3
2
1
0
reserved
reserved
sifdac_ena
Register
Name
config47
Addr
(Hex)
0x2F
Table 78. config47 Register Field Descriptions
Bit Name
Function
Default
Value
15 reserved
Reserved
0
14 titest_dieid_read When asserted, the die ID can be read out after fuse autoload is finished
0
_ena
on register 100-107. When de-asserted normal function of the registers is
read out.
13 reserved
Reserved
0
12:3 reserved
Reserved
0000000000
2 reserved
Reserved
1
1 reserved
Reserved
0
0 sifdac_ena
When asserted the DAC output is set to the value in register sifdac.
0
7.5.1.49 config48 Register – Address: 0x30, Default: 0x0000
Figure 130. config48 Register Format
15
14
13
12
11
10
9
8
sifdc
7
6
5
4
3
2
1
0
sifdc
Register
Name
config48
Addr
(Hex)
0x30
Table 79. config48 Register Field Descriptions
Bit Name
15:0 sifdc
Function
This is the value that is sent to the digital blocks when register sifdac_ena
is asserted.
Default
Value
0x0000
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