TMS320C5514_1 Datasheet, PDF (91/144 Pages) Texas Instruments – TMS320C5514 Fixed-Point Dight Signal Processor

TMS320C5514
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SPRS646A – JANUARY 2010 – REVISED MARCH 2010
Table 6-11. External Memory Interface (EMIF) Peripheral Registers ⁽¹⁾ (continued)
HEX ADDRESS
RANGE
1048h
104Ch
1060h
1064h
1065h
1068h
1069h
1070h
1071h
1074h
1075h
1078h
1079h
107Ch
107Dh
10BCh
10C0h
10C1h
10C4h
10C5h
10C8h
10C9h
10CCh
10CDh
10D0h
10D1h
10D4h
10D5h
10D8h
10D9h
10DCh
10DDh
ACRONYM
EIMSR
EIMCR
NANDFCR
NANDFSR1
NANDFSR2
PGMODECTRL1
PGMODECTRL2
NCS2ECC1
NCS2ECC2
NCS3ECC1
NCS3ECC2
NCS4ECC1
NCS4ECC2
NCS5ECC1
NCS5ECC2
NAND4BITECCLOAD
NAND4BITECC1
NAND4BITECC2
NAND4BITECC3
NAND4BITECC4
NAND4BITECC5
NAND4BITECC6
NAND4BITECC7
NAND4BITECC8
NANDERRADD1
NANDERRADD2
NANDERRADD3
NANDERRADD4
NANDERRVAL1
NANDERRVAL2
NANDERRVAL3
NANDERRVAL4
REGISTER NAME
EMIF Interrupt Mask Set Register
EMIF Interrupt Mask Clear Register
NAND Flash Control Register
NAND Flash Status Register 1
NAND Flash Status Register 2
Page Mode Control Register 1
Page Mode Control Register 2
NAND Flash CS2 1-Bit ECC Register 1
NAND Flash CS2 1-Bit ECC Register 2
NAND Flash CS3 1-Bit ECC Register 1
NAND Flash CS3 1-Bit ECC Register 2
NAND Flash CS4 1-Bit ECC Register 1
NAND Flash CS4 1-Bit ECC Register 2
NAND Flash CS5 1-Bit ECC Register 1
NAND Flash CS5 1-Bit ECC Register 2
NAND Flash 4-Bit ECC Load Register
NAND Flash 4-Bit ECC Register 1
NAND Flash 4-Bit ECC Register 2
NAND Flash 4-Bit ECC Register 3
NAND Flash 4-Bit ECC Register 4
NAND Flash 4-Bit ECC Register 5
NAND Flash 4-Bit ECC Register 6
NAND Flash 4-Bit ECC Register 7
NAND Flash 4-Bit ECC Register 8
NAND Flash 4-Bit ECC Error Address Register 1
NAND Flash 4-Bit ECC Error Address Register 2
NAND Flash 4-Bit ECC Error Address Register 3
NAND Flash 4-Bit ECC Error Address Register 4
NAND Flash 4-Bit ECC Error Value Register 1
NAND Flash 4-Bit ECC Error Value Register 2
NAND Flash 4-Bit ECC Error Value Register 3
NAND Flash 4-Bit ECC Error Value Register 4
6.9.4 EMIF Electrical Data/Timing CV_DD = 1.05 V, DV_DDEMIF = 3.3/2.75/2.5/1.8 V
Table 6-12. Timing Requirements for EMIF SDRAM/mSDRAM Interface (see Figure 6-15 and Figure 6-16)
NO.
19 t_su(DV-CLKH)
20 t_h(CLKH-DIV)
Input setup time, read data valid on EM_D[15:0] before
EM_SDCLK rising
Input hold time, read data valid on EM_D[15:0] after EM_SDCLK
rising
CV_DD = 1.05 V
DV_DDEMIF =
3.3/2.75/2.5 V
MIN MAX
3.4
1.2
CV_DD = 1.05 V
DV_DDEMIF = 1.8 V _UNIT
MIN MAX
3.4
ns
1.2
ns
Copyright © 2010, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
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