TMS320C5514_1 Datasheet, PDF (124/144 Pages) Texas Instruments – TMS320C5514 Fixed-Point Dight Signal Processor

TMS320C5514
SPRS646A – JANUARY 2010 – REVISED MARCH 2010
6.15.2 SPI Electrical Data/Timing
www.ti.com
Table 6-40. Timing Requirements for SPI Inputs (see Figure 6-29 through Figure 6-32)
NO.
5
t_C(SCLK)
Cycle time, SPI_CLK
6
t_w(SCLKH)
7
t_w(SCLKL)
Pulse duration, SPI_CLK high
Pulse duration, SPI_CLK low
Setup time, SPI_RX valid before SPI_CLK high, SPI Mode 0
Setup time, SPI_RX valid before SPI_CLK low, SPI Mode 1
8 t_{su(SRXV-SCLK) Setup time, SPI_RX valid before SPI_CLK high, SPI Mode 2}
Setup time, SPI_RX valid before SPI_CLK high, SPI Mode 3
Hold time, SPI_RX valid after SPI_CLK high, SPI Mode 0
Hold time, SPI_RX valid after SPI_CLK low, SPI Mode 1
9 t_{h(SCLK-SRXV) Hold time, SPI_RX valid after SPI_CLK low, SPI Mode 2}
Hold time, SPI_RX valid after SPI_CLK high, SPI Mode 3
CV_DD = 1.05 V
MIN
MAX
66.4 or
4P ^{(1) (2)}
30
30
16.1
16.1
16.1
16.1
0
0
0
0
CV_DD = 1.3 V
MIN
MAX
40 or
4P^{(1) (2)}
19
19
13.9
13.9
13.9
13.9
0
0
0
0
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1) P = SYSCLK period in ns. For example, when the CPU core is clocked at 100 MHz, use P = 10 ns.
(2) Use whichever value is greater.
Table 6-41. Switching Characteristics Over Recommended Operating Conditions for SPI Outputs
(see Figure 6-29 through Figure 6-32)
NO.
PARAMETER
Delay time, SPI_CLK low to SPI_TX valid, SPI
Mode 0
1 t_d(SCLK-STXV)
Delay time, SPI_CLK high to SPI_TX valid, SPI
Mode 1
Delay time, SPI_CLK high to SPI_TX valid, SPI
Mode 2
Delay time, SPI_CLK low to SPI_TX valid, SPI
Mode 3
2 t_{d(SPICS-SCLK)}
Delay time, SPI_CS active to SPI_CLK active
3
t_{oh(SCLKI-SPICSI)}
Output hold time, SPI_CS inactive to SPI_CLK
inactive
CV_DD = 1.05 V
MIN
MAX
-4.2
8.9
CV_DD = 1.3 V
UNIT
MIN
MAX
-4.9
5.3 ns
-4.2
8.9
-4.9
5.3 ns
-4.2
8.9
-4.9
5.3 ns
-4.2
8.9
t_C - 8 + D⁽¹⁾
0.5t_C - 2.2
-4.9
5.3 ns
t_C - 8 + D⁽¹⁾ ns
0.5t_C - 2.2
ns
(1) D is the programable data delay in ns. Data delay can be programmed to 0, 1, 2, or 3 SPICLK clock cycles.
SPI_CLK
SPI_TX
4
5
6
1
B0
B1
Bn-2
Bn-1
SPI_RX
SPI_CS
B0
2
B1
7
8
Bn-2
Bn-1
3
A. Character length is programmable between 1 and 32 bits; 8-bit character length shown.
B. Polarity of SPI_CSn is configurable, active-low polarity is shown.
Figure 6-29. SPI Mode 0 Transfer (CKPn = 0, CKPHn = 0)
124 Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Link(s): TMS320C5514
Copyright © 2010, Texas Instruments Incorporated