TMS320C5514_1 Datasheet, PDF (40/144 Pages) Texas Instruments – TMS320C5514 Fixed-Point Dight Signal Processor

TMS320C5514
SPRS646A – JANUARY 2010 – REVISED MARCH 2010
www.ti.com
Table 3-17. Regulators and Power Management Terminal Functions
SIGNAL
NAME
DSP_LDOO
LDOI
DSP_LDO_EN
USB_LDOO
ANA_LDOO
BG_CAP
NO.
E10
F14,
F13,
B12
D12
F12
A12
B13
TYPE ⁽¹⁾
S
S
I
S
S
O
OTHER ^{(2) (3)}
–
LDOI
DESCRIPTION
Regulators
DSP_LDO output. When enabled, this output provides a regulated 1.3 V or 1.05 V
output and up to 250 mA of current (see the I_SD parameter in Section 5.3, Electrical
Characteristics Over Recommended Ranges of Supply Voltage and Operating
Temperature). The DSP_LDO is intended to supply current to the digital core circuits
only (CV_DD) and not external devices For proper device operation, the external
decoupling capacitor of this pin should be 5uF ~ 10uF. For more detailed
information, see Section 6.3.4, Power-Supply Decoupling.
When disabled, this pin is in the high-impedance (Hi-Z) state.
LDO inputs. The LDOI pins must be connected to the same power supply source
with a voltage range of 1.8 V to 3.6 V. These pins supply power to the internal
LDOs, the bandgap reference generator circuits, and serve as the I/O supply for
some input pins.
DSP_LDO enable input. This signal is not intended to be dynamically switched.
0 = DSP_LDO is enabled. The internal POR monitors the DSP_LDOO pin voltage
and generates the internal POWERGOOD signal.
1 = DSP_LDO is disabled. The internal POR voltage monitoring is also disabled.
The internal POWERGOOD signal is forced high and the external reset signal on
the RESET pin (D6) is the only source of the device reset. Note, the device's
internal reset signal is generated as the AND of the RESET pin and the internal
POWERGOOD signal.
USB_LDO output. This output provides a regulated 1.3 V output and up to 25 mA of
current (see the I_SD parameter in Section 5.3, Electrical Characteristics Over
Recommended Ranges of Supply Voltage and Operating Temperature). For proper
device operation, this pin must be connected to a 1 mF ~ 2 mF decoupling capacitor
to V_SS. For more detailed information, see Section 6.3.4, Power-Supply Decoupling.
This LDO is intended to supply power to the USB_ V_DD1P3, USB_V_DDA1P3 pins and
not external devices.
ANA_LDO output. This output provides a regulated 1.3 V output and up to 4 mA of
current (see the I_SD parameter in Section 5.3, Electrical Characteristics Over
Recommended Ranges of Supply Voltage and Operating Temperature).
For proper device operation, this pin must be connected to an ~ 1.0 mF decoupling
capacitor to V_SS. For more detailed information, see Section 6.3.4, Power-Supply
Decoupling. This LDO is intended to supply power to the V_{DDA_ANA} and V_{DDA_PLL}
pins and not external devices.
Bandgap reference filter signal. For proper device operation, this pin needs to be
bypassed with a 0.1 mF capacitor to analog ground (V_{SSA_ANA}).
This external capacitor provides filtering for stable reference voltages & currents
generated by the bandgap circuit. The bandgap produces the references for use by
the System PLL and POR circuits.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.8.1 , Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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