TMS320VC5502_06 Datasheet, PDF (90/190 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

TMS320VC5502
Fixed-Point Digital Signal Processor
SPRS166J – APRIL 2001 – REVISED AUGUST 2006
3.12.2.4 Parallel GPIO Enable Register 1 (PGPIOEN1)
15
IO31EN
14
IO30EN
13
IO29EN
12
IO28EN
11
IO27EN
10
IO26EN
9
IO25EN
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
7
IO23EN
6
IO22EN
5
IO21EN
4
IO20EN
3
IO19EN
2
IO18EN
1
IO17EN
R/W, 0
R/W, 0
R/W, 0
LEGEND: R = Read, W = Write, n = value at reset
R/W, 0
R/W, 0
R/W, 0
R/W, 0
Figure 3-37. Parallel GPIO Enable Register 1 Layout (0x4403)
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8
IO24EN
R/W, 0
0
IO16EN
R/W, 0
Table 3-40. Parallel GPIO Enable Register 1 Bit Field Description⁽¹⁾
BIT NAME
IOxEN
BIT NO.
15-0
(1) x = value from 16 to 31
ACCESS
R/W
RESET VALUE
0000000000000000
DESCRIPTION
Enable or disable output function of the corresponding I/O pins. See
Table 3-36, TMS320VC5502 PGPIO Cross-Reference to determine
which device pins correspond to the PGPIO pins.
• IOxEN = 0:
Output function of the PGPIOx pin is disabled—i.e., the pin
cannot drive an output signal; it can only be used as an input.
When IOxEN = 0, IOxDIR must also be cleared to 0.
• IOxEN = 1:
Output function of the PGPIOx pin is enabled—i.e., the pin is
used to drive an output signal. When IOxEN = 0, IOxDIR must
also be set to 1; otherwise, the output value is undefined.
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Functional Overview
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