TMS320VC5502_06 Datasheet, PDF (82/190 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

TMS320VC5502
Fixed-Point Digital Signal Processor
SPRS166J – APRIL 2001 – REVISED AUGUST 2006
3.11.7.4 Peripheral IDLE Status Register (PISTR)
15
14
13
12
11
10
9
Reserved
MISC
EMIF
BIOST
WDT
PIO
R, 00
R, 0
R, 0
R, 0
R, 0
R, 0
7
6
5
4
3
2
1
I2C
ID
IO
SP2
SP1
SP0
TIM1
R, 0
R, 0
R, 0
R, 0
R, 0
R, 0
R, 0
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-29. Peripheral IDLE Status Register Layout (0x9401)
www.ti.com
8
URT
R, 0
0
TIM0
R, 0
BIT NAME
Reserved
MISC
EMIF
BIOST
WDT
PIO
URT
I2C
ID
IO
SP2
SP1
Table 3-31. Peripheral IDLE Status Register Bit Field Description
BIT NO.
15-14
13
12
11
10
9
8
7
6
5
4
3
ACCESS
R
R
R
R
R
R
R
R
R
R
R
R
RESET VALUE
00
0
0
0
0
0
0
0
0
0
0
0
DESCRIPTION
Reserved
MISC bit
• MISC = 0: Miscellaneous modules are active
• MISC = 1: Miscellaneous modules are disabled
Miscellaneous modules include the XBSR, TIMEOUT Error Register,
XBCR, Timer Signal Selection Register, CLKOUT Select Register,
and Clock Mode Control Register.
EMIF bit
• EMIF = 0: EMIF module is active
• EMIF = 1: EMIF module is disabled
BIOS timer bit
• BIOST = 0: DSP/BIOS timer is active
• BIOST = 1: DSP/BIOS timer is disabled
Watchdog timer bit
• WDT = 0: WDT is active
• WDT = 1: WDT is disabled
Parallel GPIO bit
• PIO = 0: Parallel GPIO is active
• PIO = 1: Parallel GPIO is disabled
UART bit
• URT = 0: UART is active
• URT = 1: UART is disabled
I2C bit
• I2C = 0: I²C is active
• I2C = 1: I²C is disabled
ID bit
• ID = 0: ID is active
• ID = 1: ID is disabled
IO bit
• IO = 0: GPIO is active
• IO = 1: GPIO is disabled
McBSP2 bit
• SP2 = 0: McBSP2 is active
• SP2 = 1: McBSP2 is disabled
McBSP1 bit
• SP1 = 0: McBSP1 is active
• SP1 = 1: McBSP1 is disabled
82
Functional Overview
Submit Documentation Feedback