TMS320VC5502_06 Datasheet, PDF (29/190 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

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TMS320VC5502
Fixed-Point Digital Signal Processor
SPRS166J – APRIL 2001 – REVISED AUGUST 2006
PIN
NAME
SP2
SP3
SCL
SDA
TIM0
TIM1
V_SS
CV_DD
PV_DD
NC
DV_DD
TCK
TDI
TDO
TMS
MULTIPLEXED
SIGNAL NAME
GPIO5
FSX2
UART.RX
FSR2
Table 2-4. Signal Descriptions (continued)
PIN
TYPE ⁽¹⁾
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
S
S
S
S
I
I
O/Z
I
OTHER ⁽²⁾
FUNCTION
F, M
The SP2 pin of Serial Port 2 serves one of two functions: GPIO5 or FSX2. The
function of the SP2 pin is determined by the state of the GPIO7 pin during reset.
The SP2 pin is set to GPIO5 if GPIO7 is low during reset. The SP2 pin is set to
FSX2 if GPIO7 is high during reset. The function of the SP2 pin will be set once the
device is taken out of reset (RESET pin transitions from a low to high state).
G, H
GPIO5. GPIO5 is selected if GPIO7 is low during reset. The GPIO5 signal is
configured as input after reset.
G, H
Frame synchronization pulse for transmitter of McBSP2. FSX2 is selected if
GPIO7 is high during reset. The FSX2 signal is configured as input after reset.
F, M
The SP3 pin of Serial Port 2 serves one of two functions: UART.RX or FSR2. The
function of the SP3 pin is determined by the state of the GPIO7 pin during reset.
The SP3 pin is set to UART.RX if GPIO7 is low during reset. The SP3 pin is set to
FSR2 if GPIO7 is high during reset. The function of the SP3 pin will be set once the
device is taken out of reset (RESET pin transitions from a low to high state).
UART receive data input. UART.RX is selected if GPIO7 is low during reset.
G, H
Frame synchronization pulse for receiver of McBSP2. FSR2 is selected if GPIO7
is high during reset. The FSR2 signal is configured as input after reset.
I²C Pins
C, F, M I²C clock bidirectional port. (Open collector I/O)
C, F, M I²C data bidirectional port. (Open collector I/O)
Timer Pins
Input/Output pin for Timer 0. The TIM0 pin can be configured as an output or an
input via the Timer Signal Selection Register (TSSR). When configured as an
output, the TIM0 pin can signal a pulse or a change of state when the Timer 0 count
F, G, H, M matches its period. When configured as an input, the TIM0 pin can be used to
provide the clock source for Timer 0 (external clock source mode) or it can be used
to start/stop the timer from counting (clock gating mode). This pin can also be used
as general-purpose I/O. The TIM0 pin is configured as an input after reset.
Input/Output pin for Timer 1. The TIM1 pin can be configured as an output or an
input via the Timer Signal Selection Register (TSSR). When configured as an
output, the TIM1 pin can signal a pulse or a change of state when the Timer 1 count
F, G, H, M matches its period. When configured as an input, the TIM1 pin can be used to
provide the clock source for Timer 1 (external clock source mode) or it can be used
to start/stop the timer from counting (clock gating mode). This pin can also be used
as general-purpose I/O. The TIM1 pin is configured as an input after reset.
Supply Pins
Digital Ground.Dedicated ground for the device.
Digital Power, + V_DD. Dedicated power supply for the core CPU.
Digital Power, + V_DD. Dedicated power supply for the PLL module.
No Connect
Digital Power, + V_DD. Dedicated power supply for the I/O pins.
Test Pins
IEEE standard 1149.1 test clock. TCK is normally a free-running clock signal with
a 50% duty cycle. The changes on test access port (TAP) of input signals TMS and
C, J
TDI are clocked into the TAP controller, instruction register, or selected test data
register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur
on the falling edge of TCK. Refer to Section 3.18, Notice Concerning TCK, for
important information regarding this pin.
J
IEEE standard 1149.1 test data input. Pin with internal pullup device. TDI is
clocked into the selected register (instruction or data) on a rising edge of TCK.
IEEE standard 1149.1 test data output. The contents of the selected register
(instruction or data) are shifted out of TDO on the falling edge of TCK. TDO is in the
high-impedance state except when the scanning of data is in progress.
J
IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial
control input is clocked into the TAP controller on the rising edge of TCK.
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