TMS320VC5502_06 Datasheet, PDF (4/190 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

TMS320VC5502
Fixed-Point Digital Signal Processor
SPRS166J – APRIL 2001 – REVISED AUGUST 2006
www.ti.com
3.13 External Bus Control Register ............................................................................................ 96
3.13.1 External Bus Control Register (XBCR) ....................................................................... 97
3.14 Internal Ports and System Registers .................................................................................... 98
3.14.1 XPORT Interface ................................................................................................ 98
3.14.2 DPORT Interface............................................................................................... 100
3.14.3 IPORT Interface ................................................................................................ 102
3.14.4 System Configuration Register (CONFIG).................................................................. 103
3.14.5 Time-Out Control Register (TOCR).......................................................................... 104
3.15 CPU Memory-Mapped Registers ....................................................................................... 105
3.16 Peripheral Registers...................................................................................................... 107
3.17 Interrupts ................................................................................................................... 120
3.17.1 IFR and IER Registers ....................................................................................... 121
3.17.2 Interrupt Timing ................................................................................................ 122
3.17.3 Interrupt Acknowledge......................................................................................... 122
3.18 Notice Concerning TCK.................................................................................................. 123
4 Support ........................................................................................................................... 125
4.1 Notices Concerning JTAG (IEEE 1149.1) Boundary Scan Test Capability ....................................... 125
4.1.1 Initialization Requirements for Boundary Scan Test ...................................................... 125
4.1.2 Boundary Scan Description Language (BSDL) Model .................................................... 125
4.2 Documentation Support .................................................................................................. 125
4.3 Device and Development-Support Tool Nomenclature .............................................................. 127
5 Specifications .................................................................................................................. 128
5.1 Electrical Specifications .................................................................................................. 128
5.2 Absolute Maximum Ratings Over Operating Case Temperature Range
(Unless Otherwise Noted) ............................................................................................... 128
5.3 Recommended Operating Conditions.................................................................................. 128
5.4 Electrical Characteristics Over Recommended Operating Case Temperature Range
(Unless Otherwise Noted) ............................................................................................... 129
5.5 Timing Parameter Symbology........................................................................................... 130
5.6 Clock Options ............................................................................................................. 131
5.6.1 Internal System Oscillator With External Crystal........................................................... 131
5.6.2 Layout Considerations......................................................................................... 132
5.6.3 Clock Generation in Bypass Mode (APLL Disabled) ...................................................... 133
5.6.4 Clock Generation in Lock Mode (APLL Synthesis Enabled) ............................................. 134
5.6.5 EMIF Clock Options ........................................................................................... 135
5.7 Memory Timings .......................................................................................................... 137
5.7.1 Asynchronous Memory Timings.............................................................................. 137
5.7.2 Programmable Synchronous Interface Timings ........................................................... 140
5.7.3 Synchronous DRAM Timings................................................................................. 143
5.8 HOLD/HOLDA Timings .................................................................................................. 148
5.9 Reset Timings ............................................................................................................. 149
5.10 External Interrupt and Interrupt Acknowledge (IACK) Timings ..................................................... 151
5.11 XF Timings................................................................................................................. 152
5.12 General-Purpose Input/Output (GPIOx) Timings ..................................................................... 153
5.13 Parallel General-Purpose Input/Output (PGPIOx) Timings.......................................................... 154
5.14 TIM0/TIM1/WDTOUT Timings .......................................................................................... 155
5.14.1 TIM0/TIM1/WDTOUT Timer Pin Timings ................................................................... 155
5.14.2 TIM0/TIM1/WDTOUT General-Purpose I/O Timings...................................................... 156
5.14.3 TIM0/TIM1/WDTOUT Interrupt Timings..................................................................... 158
5.15 Multichannel Buffered Serial Port (McBSP) Timings................................................................. 159
5.15.1 McBSP Transmit and Receive Timings ..................................................................... 159
5.15.2 McBSP General-Purpose I/O Timings ...................................................................... 162
5.15.3 McBSP as SPI Master or Slave Timings.................................................................... 163
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