TMS320DM643 Datasheet, PDF (90/160 Pages) Texas Instruments – Video/Imaging Fixed-Point Digital Signal Processo

TMS320DM643
Video/Imaging Fixed-Point Digital Signal Processor
SPRS269A – FEBRUARY 2005 – REVISED APRIL 2005
www.ti.com
AECLKOUTx
READ latency = 2
ACEx
ABE[7:0]
AEA[22:3]
AED[63:0]
AARE/ASDCAS/ASADS/ASRE^(C)
1
2
BE1
4
EA1
8
1
BE2
BE3
EA2
EA3
6
Q1
BE4
EA4
7
Q2
3
5
Q3
Q4
8
9
9
AAOE/ASDRAS/ASOE^(C)
AAWE/ASDWE/ASWE^(C)
A. The read latency and the length of ACEx assertion are programmable via the SYNCRL and CEEXT fields, respectively, in the EMIFA CE
Space Secondary Control register (CExSEC). In this figure, SYNCRL = 2 and CEEXT = 0.
B. The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC):
− Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency
− Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency
− ACEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been
issued (CEEXT = 0). For synchronous FIFO interface with glue, ACEx is active when ASOE is active (CEEXT = 1).
− Function of ASADS/ASRE (RENEN): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect cycles
(RENEN = 0). For FIFO interface, ASADS/ASRE acts as ASRE with NO deselect cycles (RENEN = 1).
− Synchronization clock (SNCCLK): Synchronized to AECLKOUT1 or AECLKOUT2
C. AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and AAWE/ASDWE/ASWE operate as ASADS/ASRE, ASOE, and ASWE, respectively,
during programmable synchronous interface accesses.
Figure 5-19. Programmable Synchronous Interface Read Timing for EMIFA (With Read Latency = 2) ^(A)(B)
90
DM643 Peripheral Information and Electrical Specifications