TMS320DM643 Datasheet, PDF (63/160 Pages) Texas Instruments – Video/Imaging Fixed-Point Digital Signal Processo

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TMS320DM643
Video/Imaging Fixed-Point Digital Signal Processor
SPRS269A – FEBRUARY 2005 – REVISED APRIL 2005
4.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating
Case Temperature (Unless Otherwise Noted)
PARAMETER
TEST CONDITIONS ⁽¹⁾
MIN TYP
MAX UNIT
V_OH High-level output voltage
DV_DD = MIN, I_OH = MAX
2.4
V_OL Low-level output voltage
DV_DD = MIN, I_OL = MAX
V_I = V_SS to DV_DD no opposing internal
resistor
V
0.4 V
±10 uA
I_I
Input current
V_I = V_SS to DV_DD opposing internal pullup
resistor ⁽²⁾
50 100
150 uA
V_I = V_SS to DV_DD opposing internal
pulldown resistor ⁽²⁾
–150 –100
–50 uA
EMIF, CLKOUT4, CLKOUT6, EMUx
–16 mA
I_OH High-level output current
Video Ports, Timer, TDO, GPIO
(Excluding GP0[2:1]), McBSP
–8 mA
HPI
–0.5 mA
EMIF, CLKOUT4, CLKOUT6, EMUx
16 mA
I_OL
Low-level output current
Video Ports, Timer, TDO, GPIO
(Excluding GP0[2:1]), McBSP
SCL0 and SDA0
8 mA
3 mA
HPI
1.5 mA
I_OZ
Off-state output current
I_CDD Core supply current⁽³⁾
I_DDD I/O supply current⁽³⁾
C_i
Input capacitance
C_o
Output capacitance
V_O = DV_DD or 0 V
CV_DD = 1.4 V, CPU clock = 600 MHz
CV_DD = 1.2 V, CPU clock = 500 MHz
DV_DD = 3.3 V, CPU clock = 600 MHz
DV_DD = 3.3 V, CPU clock = 500 MHz
±10 uA
890
mA
620
mA
210
mA
165
mA
10 pF
10 pF
(1) For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table.
(2) Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor.
(3) Measured with average activity (50% high/50% low power) at 25°C case temperature and 133-MHz EMIF for -600 speed (100-MHz
EMIF for -500 speed). This model represents a device performing high-DSP-activity operations 50% of the time, and the remainder
performing low-DSP-activity operations. The high/low-DSP-activity models are defined as follows:
• High-DSP-Activity Model:
– CPU: 8 instructions/cycle with 2 LDDW instructions [L1 Data Memory: 128 bits/cycle via LDDW instructions;
L1 Program Memory: 256 bits/cycle; L2/EMIF EDMA: 50% writes, 50% reads to/from SDRAM (50% bit-switching)]
– McBSP: 1 channel at 2.048 MHz
– Timers: 2 timers at maximum rate
• Low-DSP-Activity Model:
– CPU: 2 instructions/cycle with 1 LDH instruction [L1 Data Memory: 16 bits/cycle; L1 Program Memory: 256 bits per 4 cycles;
L2/EMIF EDMA: None]
– McBSP: 1 channel at 2.048 MHz
– Timers: 2 timers at maximum rate
The actual current draw is highly application-dependent. For more details on core and I/O activity, refer to the TMS320DMx Power
Consumption Summary application report (literature number SPRA962).
Device Operating Conditions
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