TMS320DM643 Datasheet, PDF (114/160 Pages) Texas Instruments – Video/Imaging Fixed-Point Digital Signal Processo

TMS320DM643
Video/Imaging Fixed-Point Digital Signal Processor
SPRS269A – FEBRUARY 2005 – REVISED APRIL 2005
5.11.2 Host-Port Interface (HPI) Electrical Data/Timing
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Table 5-38. Timing Requirements for Host-Port Interface Cycles⁽¹⁾⁽²⁾ (see Figure 5-38 through Figure 5-45)
–500
NO.
–600
MIN MAX
1
t_{su(SELV-HSTBL)}
2
t_{h(HSTBL-SELV)}
3
t_w(HSTBL)
4
t_w(HSTBH)
10 t_{su(SELV-HASL)}
11 t_h(HASL-SELV)
12 t_{su(HDV-HSTBH)}
13 t_h(HSTBH-HDV)
14 t_{h(HRDYL-HSTBL)}
Setup time, select signals⁽³⁾ valid before HSTROBE low
Hold time, select signals⁽³⁾ valid after HSTROBE low
Pulse duration, HSTROBE low
Pulse duration, HSTROBE high between consecutive accesses
Setup time, select signals⁽³⁾ valid before HAS low
Hold time, select signals⁽³⁾ valid after HAS low
Setup time, host data valid before HSTROBE high
Hold time, host data valid after HSTROBE high
Hold time, HSTROBE low after HRDY low. HSTROBE should not be inactivated
until HRDY is active (low); otherwise, HPI writes will not complete properly.
5
2.4
4P ⁽⁴⁾
4P
5
2
5
2.8
2
18 t_{su(HASL-HSTBL)}
Setup time, HAS low before HSTROBE low
2
19 t_{h(HSTBL-HASL)}
Hold time, HAS low after HSTROBE low
2.1
(1) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
(2) P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
(3) Select signals include: HCNTL[1:0] and HR/W. For HPI16 mode only, select signals also include HHWIL.
(4) Select the parameter value of 4P or 12.5 ns, whichever is larger.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 5-39. Switching Characteristics Over Recommended Operating Conditions During Host-Port
Interface Cycles⁽¹⁾⁽²⁾ (see Figure 5-38 through Figure 5-45)
NO.
PARAMETER
–500
–600
UNIT
MIN
MAX
6
t_{d(HSTBL-HRDYH)}
Delay time, HSTROBE low to HRDY high⁽³⁾
1.3 4P + 8
ns
7
t_{d(HSTBL-HDLZ)}
Delay time, HSTROBE low to HD low impedance for an HPI read
2
ns
8
t_d(HDV-HRDYL)
Delay time, HD valid to HRDY low
3
ns
9
t_{oh(HSTBH-HDV)}
Output hold time, HD valid after HSTROBE high
1.5
ns
15 t_{d(HSTBH-HDHZ)}
Delay time, HSTROBE high to HD high impedance
12
ns
16 t_d(HSTBL-HDV)
Delay time, HSTROBE low to HD valid (HPI16 mode, 2nd half-word only)
4P + 8
ns
(1) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
(2) P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
(3) This parameter is used during HPID reads and writes. For reads, at the beginning of a word transfer (HPI32) or the first half-word
transfer (HPI16) on the falling edge of HSTROBE, the HPI sends the request to the EDMA internal address generation hardware, and
HRDY remains high until the EDMA internal address generation hardware loads the requested data into HPID. For writes, HRDY goes
high if the internal write buffer is full.
114 DM643 Peripheral Information and Electrical Specifications