TMS320DM643 Datasheet, PDF (142/160 Pages) Texas Instruments – Video/Imaging Fixed-Point Digital Signal Processo

TMS320DM643
Video/Imaging Fixed-Point Digital Signal Processor
SPRS269A – FEBRUARY 2005 – REVISED APRIL 2005
www.ti.com
Table 5-66. Timing Requirements for EMAC MII Receive 10/100 Mbit/s⁽¹⁾ (see Figure 5-59)
NO.
1 t_{su(MRXD-MRCLKH)}
Setup time, receive selected signals valid before MRCLK high
2 t_{h(MRCLKH-MRXD)}
Hold time, receive selected signals valid after MRCLK high
(1) Receive selected signals include: MRXD3-MRXD0, MRXDV, and MRXER.
–500
–600
MIN MAX
8
8
UNIT
ns
ns
MRXD3–MRXD0 is driven by the PHY on the falling edge of MRCLK. MRXD3–MRXD0 timing must be
met during clock periods when MRXDV is asserted. MRXDV is asserted and deasserted by the PHY on
the falling edge of MRCLK. MRXER is driven by the PHY on the falling edge of MRCLK (xx = 00–01).
1
2
MRCLK (Input)
MRXD3−MRXD0,
MRXDV, MRXER (Inputs)
Figure 5-59. EMAC Receive Interface Timing
Table 5-67. Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit
10/100 Mbit/s⁽¹⁾ (see Figure 5-60)
NO.
1 t_{d(MTCLKH-MTXD)}
Delay time, MTCLK high to transmit selected signals valid
(1) Transmit selected signals include: MTXD3–MTXD0, and MTXEN.
–500
–600
MIN MAX
5
25
UNIT
ns
MTXD3–MTXD0 is driven by the reconciliation sublayer synchronous to the MTCLK. MTXEN is asserted
and deasserted by the reconciliation sublayer synchronous to the MTCLK rising edge.
1
MTCLK (Input)
MTXD3−MTXD0,
MTXEN (Outputs)
Figure 5-60. EMAC Transmit Interface Timing
142 DM643 Peripheral Information and Electrical Specifications