TCA8418E Datasheet, PDF (9/35 Pages) Texas Instruments – I2C CONTROLLED KEYPAD SCAN IC WITH INTEGRATED ESD PROTECTION

TCA8418E
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SCPS222B – MAY 2010 – REVISED SEPTEMBER 2010
V_CC
Ramp-Down
V_IN drops below POR levels
V_{CC_TRR_VPOR50}
Ramp-Up
V_{CC_FT}
Time to Re-Ramp
V_{CC_RT}
Time
Figure 2. V_CC is Lowered Below the POR Threshold, Then Ramped Back Up to V_CC
Table 2 specifies the performance of the power-on reset feature for TCA8418E for both types of power-on reset.
Table 2. RECOMMENDED SUPPLY SEQUENCING AND RAMP RATES⁽¹⁾
V_{CC_FT}
V_{CC_RT}
V_{CC_TRR_GND}
V_{CC_TRR_POR50}
V_{CC_GH}
V_{CC_GW}
V_PORF
V_PORR
PARAMETER
Fall rate
Rise rate
Time to re-ramp (when V_CC drops to GND)
Time to re-ramp (when V_CC drops to V_{POR_MIN} – 50 mV)
Level that V_CCP can glitch down to, but not cause a functional
disruption when V_{CCX_GW} = 1 ms
Glitch width that will not cause a functional disruption when
V_{CCX_GH} = 0.5 × V_CCx
Voltage trip point of POR on falling V_CC
Voltage trip point of POR on rising V_CC
See Figure 1
See Figure 1
See Figure 1
See Figure 2
See Figure 3
See Figure 3
MIN TYP
1
0.01
0.001
0.001
MAX
100
100
UNIT
ms
ms
ms
ms
1.2 V
0.767
1.033
ms
1.144 V
1.428 V
(1) T_A = –40°C to 85°C (unless otherwise noted)
Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width
(V_{CC_GW}) and height (V_{CC_GH}) are dependent on each other. The bypass capacitance, source impedance, and
device impedance are factors that affect power-on reset performance. Figure 3 and Table 2 provide more
information on how to measure these specifications.
V_CC
V_{CC_GH}
Time
V_{CC_GW}
Figure 3. Glitch Width and Glitch Height
V_POR is critical to the power-on reset. V_POR is the voltage level at which the reset condition is released and all the
registers and the I²C/SMBus state machine are initialized to their default states. The value of V_POR differs based
on the V_CC being lowered to or from 0. Figure 4 and Table 2 provide more details on this specification.
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