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TCA8418E Datasheet, PDF (18/35 Pages) Texas Instruments – I2C CONTROLLED KEYPAD SCAN IC WITH INTEGRATED ESD PROTECTION | |||
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TCA8418E
SCPS222B â MAY 2010 â REVISED SEPTEMBER 2010
www.ti.com
ADDRESS REGISTER NAME(1)
REGISTER DESCRIPTION
0Ã10
Unlock2
Unlock key 2
BIT
7
6
5
4
3
2
1
0
UK2_ UK2_ UK2 UK2_ UK2_ UK2 UK2_ UK2
7
6
_5
4
3
_2
1
_0
UK1[6:0] contains the key number used to unlock key 1
UK2[6:0] contains the key number used to unlock key 2
A â0â in either register means it is disabled. It lasts up to 7 seconds. Needs a second timer up to 31 seconds?
The keypad lock interrupt mask timer generates a first interrupt (K_INT) and then waits for a programmed time
before generating a second interrupt. A second interrupt can only be generated when a timer is enabled due to
an unlock sequence being pressed. The second interrupt is a key lock interrupt. When the interrupt mask timer is
disabled (â0â), a key lock interrupt will trigger only when the correct and complete unlock sequence is completed.
GPIO Interrupt Status Registers, GPIO_INT_STAT1â3 (Address 0Ã11â0Ã13)
These registers are used to check GPIO interrupt status and are cleared on read.
GPIO Data Status Registers, GPIO_DAT_STAT1â3 (Address 0Ã14â0Ã16)
These registers show GPIO state when read for inputs and outputs.
GPIO Data Out Registers, GPIO_DAT_OUT1â3 (Address 0Ã17â0Ã19)
These registers contain GPIO data to be written to GPIO out driver; inputs are not affected. This is needed so
that the value can be written prior to being set as an output.
GPIO Interrupt Enable Registers, GPIO_INT_EN1â3 (Address 0Ã1Aâ0Ã1C)
These registers enable interrupts for GP inputs only.
Keypad or GPIO Selection Registers, KP_GPIO1â3 (Address 0Ã1Dâ0Ã1F)
A bit value of '0' in any of the unreserved bits puts the corresponding pin in GPIO mode. A '1' in any of these bits
puts the pin in keyscan mode and configured as a row or column accordingly.
GPI Event Mode Registers, GPI_EM1â3 (Address 0Ã20â0Ã22)
A bit value of '0' in any of the unreserved bits indicates that it is not part of the event FIFO. A '1' in any of these
bits means it is part of the event FIFO.
GPIO Data Direction Registers, GPIO_DIR1â3 (Address 0Ã23â0Ã25)
A bit value of '0' in any of the unreserved bits sets the corresponding pin as an input. A '1' in any of these bits
sets the pin as an output.
GPIO Edge/Level Detect Registers, GPIO_INT_LVL1â3 (Address 0Ã26â0Ã28)
A bit value of '0' indicates that interrupt will be triggered on a high-to-low transition for the inputs in GPIO mode.
A bit value of '1' indicates that interrupt will be triggered on a low-to-high value for the inputs in GPIO mode.
Debounce Disable Registers, DEBOUNCE_DIS1â3 (Address 0Ã29â0Ã2B)
This is for pins configured as inputs. A bit value of â0â in any of the unreserved bits disables the debounce while a
bit value of â1â enables the debounce.
ADDRESS REGISTER NAME(1)
REGISTER DESCRIPTION
0Ã2B
DEBOUNCE_DIS 3
Debounce disable
0: enabled
1: disabled
(1) Only KEY_EVENT_A register is shown
7
6
N/A
BIT
5
4
3
2
1
0
N/A
0
N/A
0
N/A
0
C9DD
0
C8D
D
0
18
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