TCA8418E Datasheet, PDF (6/35 Pages) Texas Instruments – I2C CONTROLLED KEYPAD SCAN IC WITH INTEGRATED ESD PROTECTION

TCA8418E
SCPS222B – MAY 2010 – REVISED SEPTEMBER 2010
www.ti.com
I²C INTERFACE TIMING REQUIREMENTS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 13)
STANDARD MODE
I²C BUS
FAST MODE
I²C BUS
FAST MODE PLUS (FM+)
I²C BUS
f_scl
I²C clock frequency
t_sch
I²C clock high time
t_scl
I²C clock low time
t_sp
I²C spike time
t_sds
I²C serial data setup time
t_sdh
I²C serial data hold time
t_icr
I²C input rise time
t_icf
I²C input fall time
t_ocf
I²C output fall time; 10 pF to 400 pF bus
t_buf
I²C bus free time between Stop and
Start
t_sts
I²C Start or repeater Start condition
setup time
t_sth
I²C Start or repeater Start condition hold
time
t_sps
I²C Stop condition setup time
t_vd(data)
Valid data time; SCL low to SDA output
valid
MIN
MAX
MIN
MAX
0
100
0
400
4
0.6
4.7
1.3
50
50
250
100
0
0
1000 20 + 0.1C_b ⁽¹⁾
300
300 20 + 0.1C_b ⁽¹⁾
300
300 20 + 0.1C_b ⁽¹⁾
300
4.7
1.3
4.7
0.6
4
4
1
0.6
0.6
0.9
MIN
MAX
0
1000
0.26
0.5
50
50
0
120
120
120
0.5
0.26
0.26
0.26
0.45
UNIT
kHz
ms
ms
ns
ns
ns
ns
ns
ms
ms
ms
ms
ms
ms
t_vd(ack)
Valid data time of ACK condition; ACK
signal from SCL low to SDA (out) low
1
0.9
0.45 ms
(1) C_b = total capacitance of one bus line in pF
RESET TIMING REQUIREMENTS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 16)
STANDARD MODE, FAST
MODE, FAST MODE PLUS
(FM+)
I²C BUS
t_W
t_REC
t_RESET
Reset pulse duration
Reset recovery time
Time to reset
MIN
120 ⁽¹⁾
120 ⁽¹⁾
120 ⁽¹⁾
MAX
UNIT
ms
ms
ms
(1) The GPIO debounce circuit uses each GPIO input which passes through a two-stage register circuit. Both registers are clocked by the
same clock signal, presumably free-running, with a nominal period of 50uS. When an input changes state, the new state is clocked into
the first stage on one clock transition. On the next same-direction transition, if the input state is still the same as the previously clocked
state, the signal is clocked into the second stage, and then on to the remaining circuits. Since the inputs are asynchronous to the clock,
it will take anywhere from zero to 50 msec after the input transition to clock the signal into the first stage. Therefore, the total debounce
time may be as long as 100 msec. Finally, to account for a slow clock, the spec further guard-banded at 120 msec.
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