TCA8418E Datasheet, PDF (20/35 Pages) Texas Instruments – I2C CONTROLLED KEYPAD SCAN IC WITH INTEGRATED ESD PROTECTION

TCA8418E
SCPS222B – MAY 2010 – REVISED SEPTEMBER 2010
Figure 8. Typical Application
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Table 5. Key Value Assignment
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9
R0 1 2
3
45
6
7
8
9 10
R1 11 12 13 14 15 16 17 18 19 20
R2 21 22 23 24 25 26 27 28 29 30
R3 31 32 33 34 35 36 37 38 39 40
R4 41 42 43 44 45 46 47 48 49 50
R5 51 52 53 54 55 56 57 58 59 60
R6 61 62 63 64 65 66 67 68 69 70
R7 71 72 73 74 75 76 77 78 79 80
The 18 GPIOs can be configured to support up to 80 keys. The GPIOs are programmed into rows (maximum of
8) and columns (maximum of 10) to support a keypad. This is done through writing to “Keypad or GPIO
Selection” registers (0x1D – 0x1F). The keypad in idle mode will be configured as Columns being driven low and
Rows as inputs with pull-ups.
When there is a key press or multiple key presses (Short between Column and Row), it will trigger an internal
state machine interrupt. The row that has a pressed key can be determined through reading the “GPIO Data
Status” registers (0x14-0x16).After that, the state machine starts a keyscan cycle to determine the column of the
key that was pressed. The state machine sets one column as an output low and all other columns as high. The
state machine will then walk a zero across the applicable row to determine what keys are being pressed.
Once a key has been pressed for 25 ms, the state machine will set the appropriate key/s in the Key Event Status
register with the key-pressed bit set (bit 7). If the K_IEN is set it will then set KE_INT and generate an interrupt to
the host processor. The state machine will continue to poll while there are keys pressed. If a key/s that was in
the key pressed register is released for 25 ms or greater, the state machine will set the appropriate keys in the
Key Event Status register with the key pressed bit cleared. If K_IEN is set it will set the K_INT and generate an
interrupt to the host processor.
After receiving an interrupt, the host processor will first read the Interrupt Status register to determine what
interrupt caused the processor interrupt. It will then read the Key Event Register to see what keys where
pressed/released (Bits will then automatically clear on read in those registers). The processor will then write a 1
to the interrupt bit in the interrupt register to clear it and release the host interrupt to the processor. The
processor can see the status of what keys are pressed at any point by reading the KEY_EVENT_A register
(FIFO).
See Key Event Registers (FIFO) for more information.
When all Key_Event Registers are full, any additional events with set the OVR_FLOW_INT bit to 1. This will also
trigger an interrupt to the processor. When the FIFO is not full, new events are added to the next empty
Key_Event register in line. The OVR_FLOW_M bit sets the mode of operation during overflows. Clearing this bit
will cause new incoming events to be ignored and discarded. Setting this bit will overwrite old data with new data
starting with the first event.
Keypad Lock/Unlock
This user can lock the keypad through the lock/unlock feature in this device. Once the keypad is locked, it can
prevent the generation of key event interrupts and recorded key events. The unlock keys can be programmed
with any value of the keys in the keypad matrix or any GPI values that are part of the key event table. When the
keypad lock interrupt mask timer is enabled, the user will need to press two specific keys before an keylock
interrupt is generated or keypad events are recorded. After the keypad is locked, a key event interrupt is
generated any time a user presses a key. This first interrupt also triggers the processor to turn on the LCD and
display the unlock message. The processor will then read the lock status register to see if the keypad is
unlocked. The next interrupt (keylock interrupt) will not be generated unless both unlock keys sequences are
correct. If correct Unlock keys are not pressed before the mask timer expires, the state machine will start over
again.
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