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DS90CF366 Datasheet, PDF (9/20 Pages) Texas Instruments – 20 to 85 MHz Shift Clock Support, Rx Power Consumption <142 mW (typ) @85MHz Grayscale
DS90CF366, DS90CF386
www.ti.com
SNLS055I – NOVEMBER 1999 – REVISED APRIL 2013
DS90CF386 DGG0056A Package PIN DESCRIPTIONS—24-Bit FPD Link Receiver
Pin Name
I/O No.
Description
RxIN+
I 4 Positive LVDS differentiaI data inputs.
RxIN−
I 4 Negative LVDS differential data inputs.
RxOUT
O 28 TTL level data outputs. This includes: 8 Red, 8 Green, 8 Blue, and 3 control lines—FPLINE, FPFRAME,
DRDY (also referred to as HSYNC, VSYNC, Data Enable).
RxCLK IN+
I 1 Positive LVDS differential clock input.
RxCLK IN−
I 1 Negative LVDS differential clock input.
RxCLK OUT
O 1 TTL Ievel clock output. The falling edge acts as data strobe.
PWR DOWN
I 1 TTL level input. When asserted (low input) the receiver outputs are low.
V CC
GND
I 4 Power supply pins for TTL outputs.
I 5 Ground pins for TTL outputs.
PLL V CC
PLL GND
I 1 Power supply for PLL.
I 2 Ground pin for PLL.
LVDS V CC
LVDS GND
I 1 Power supply pin for LVDS inputs.
I 3 Ground pins for LVDS inputs.
DS90CF366 DGG0048A Package PIN DESCRIPTIONS—18-Bit FPD Link Receiver
Pin Name
I/O No.
Description
RxIN+
I 3 Positive LVDS differentiaI data inputs.
RxIN−
I 3 Negative LVDS differential data inputs.
RxOUT
O 21 TTL level data outputs. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines—FPLINE, FPFRAME,
DRDY (also referred to as HSYNC, VSYNC, Data Enable).
RxCLK IN+
I 1 Positive LVDS differential clock input.
RxCLK IN−
I 1 Negative LVDS differential clock input.
RxCLK OUT
O 1 TTL Ievel clock output. The falling edge acts as data strobe.
PWR DOWN
I 1 TTL level input. When asserted (low input) the receiver outputs are low.
V CC
GND
I 4 Power supply pins for TTL outputs.
I 5 Ground pins for TTL outputs.
PLL V CC
PLL GND
I 1 Power supply for PLL.
I 2 Ground pin for PLL.
LVDS V CC
LVDS GND
I 1 Power supply pin for LVDS inputs.
I 3 Ground pins for LVDS inputs.
Copyright © 1999–2013, Texas Instruments Incorporated
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