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DS90CF366 Datasheet, PDF (10/20 Pages) Texas Instruments – 20 to 85 MHz Shift Clock Support, Rx Power Consumption <142 mW (typ) @85MHz Grayscale
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DS90CF366, DS90CF386
SNLS055I – NOVEMBER 1999 – REVISED APRIL 2013
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DS90CF386 — 64 ball NFBGA package PIN DESCRIPTIONS — FPD Link Receiver
Pin Name
I/O No.
Description
RxIN+
I 4 Positive LVDS differentiaI data inputs.
RxIN−
I 4 Negative LVDS differential data inputs.
RxOUT
O 28 TTL level data outputs. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines—FPLINE, FPFRAME,
DRDY (also referred to as HSYNC, VSYNC, Data Enable).
RxCLK IN+
I 1 Positive LVDS differential clock input.
RxCLK IN−
I 1 Negative LVDS differential clock input.
FPSHIFT OUT
O 1 TTL Ievel clock output. The falling edge acts as data strobe. Pin name RxCLK OUT.
PWR DOWN
I 1 TTL level input. When asserted (low input) the receiver outputs are low.
VCC
GND
I 4 Power supply pins for TTL outputs.
I 5 Ground pins for TTL outputs.
PLL VCC
PLL GND
I 1 Power supply for PLL.
I 2 Ground pin for PLL.
LVDS VCC
LVDS GND
I 1 Power supply pin for LVDS inputs.
I 3 Ground pins for LVDS inputs.
NC
6 Pins not connected.
DS90CF386 Pin Descriptions — 64 ball NFBGA Package — FPD Link Receiver
By Pin
By Pin Type
Pin
Pin Name
Type
Pin
Pin Name
Type
A1
RxOUT17
O
A4
GND
G
A2
VCC
P
B1
GND
G
A3
RxOUT15
O
B6
GND
G
A4
GND
G
D8
GND
G
A5
RxOUT12
O
E3
GND
G
A6
RxOUT8
O
E5
LVDS GND
G
A7
RxOUT7
O
G3
LVDS GND
G
A8
RxOUT6
O
G7
LVDS GND
G
B1
GND
G
H5
LVDS GND
G
B2
NC
F6
PLL GND
G
B3
RxOUT16
O
G8
PLL GND
G
B4
RxOUT11
O
E6
PWR DWN
I
B5
VCC
P
H6
RxCLKIN-
I
B6
GND
G
H7
RxCLKIN+
I
B7
RxOUT5
O
H2
RxIN0-
I
B8
RxOUT3
O
H3
RxIN0+
I
C1
RxOUT21
O
F4
RxIN1-
I
C2
NC
G4
RxIN1+
I
C3
RxOUT18
O
G5
RxIN2-
I
C4
RxOUT14
O
F5
RxIN2+
I
C5
RxOUT9
O
G6
RxIN3-
I
C6
RxOUT4
O
H8
RxIN3+
I
C7
NC
E7
RxCLKOUT
O
C8
RxOUT1
O
E8
RxOUT0
O
D1
VCC
P
C8
RxOUT1
O
D2
RxOUT20
O
D5
RxOUT10
O
D3
RxOUT19
O
B4
RxOUT11
O
D4
RxOUT13
O
A5
RxOUT12
O
D5
RxOUT10
O
D4
RxOUT13
O
10
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